Puligandla Viswanadham
Nokia
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Featured researches published by Puligandla Viswanadham.
electronic components and technology conference | 2001
Nael Hannan; Puligandla Viswanadham
Filling the interspace between package and the printed wiring board (PWB), namely underfilling, was demonstrated to yield dramatic reliability improvement in mechanical shock and bending (flexing) stresses of most chip scale package (CSP) assemblies in mobile phone applications. However, rework of defective CSPs cannot be performed after the underfill operation. The need for the ability to rework underfills has, in recent years, resulted in developmental efforts to formulate materials that can easily be reworked as well as provide requisite product reliability. The implementation of reworkable underfills involves: choice of proper material, development of an acceptable process, and a verification of reliability. In this paper are discussed some of the critical issues that need to be considered in the evaluation of reworkable underfill materials and their application in portable communication products.
intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2006
Mohammad M. Hossain; F. Zahedi; Dereje Agonafer; S.O. Dunford; Puligandla Viswanadham
Tin/silver/copper (SAC) solder alloys have been introduced as primary alternatives to the eutectic tin-lead solder. SAC alloys are relatively new alloy systems in packaging applications and existing studies are limited and confined mainly to the materials, assembly process, and finite element modeling. It is essential to conduct research focusing on the material aspects of the SAC alloy coupled with its effect on reliability using both experimental methods and finite element simulations. The focus of this paper is experimental study of lead-free solder package test boards under cyclic bend load and drop impact loading. Amkor CTBGA 288 components were assembled on eight layer test boards (JESD22-B111) with Sn/Ag/Cu (95.5Sn3.8Ag0.7Cu) solder using three different PWB pad surface finishes to study the effect of the surface finish on the interconnect reliability. The pad finishes were immersion Au, immersion Ag and the organic solder preservative (OSP). The test specimens were subjected to cyclic bend fatigue and board level drop tests. Strain gage measurements were taken at numerous locations across populated and unpopulated PWBs and the data were used to create contour plots to identify variations in stress due to location and localized stiffness due to components. Results are presented with failure mode and analysis of those packages with different pad finishes and loading conditions. Finite element models were also created for the bend test boards to investigate the stress distribution and stress concentration
electronic components and technology conference | 2003
Weiqun Peng; S. Dunford; Puligandla Viswanadham; S. Quander
The influence of gold plating on leadless organic and ceramic chip carrier component terminals on the performance of the Sn-2.5Ag-O.SCu-0.5Sb solder joints was investigated by metallurgical analysis. The microstructure of the solder joint was examined as reflowed, after 200, and 500 thermal cycles, respectively, using scanning electron microscopy. Comparisons were made with Sn-Pb-2Ag solderjoints. Microstructural and performance implementation of SnAg-Cu-Sb solder in the gold content range of 1.5-7 wt. % were investigated. Gold content increase in solder joints generally results in an increase in AdSn intermetallic compound (IMC) and some times formation of irregular shaped voids. In some cases up to 17 wt. % Au content was found in solder joint due to component termination construction and plating thickness. Coefficient of thermal expansion and package size influenced solder joint crack development and propagation. The lead-free solder and SnPb-2Ag solder joints exhibited different failure mechanizms in the presence of gold. Cracks in the lead-free joints propagated along the boundaries of Au-Sn and Ag-Sn intermetallics, while they propagated through the Pb-rich layer at the solder-component interface in the Sn-Pb-2Ag solder joints. The microstructure of the lead-free solder was more stable through thermal cycling than in the case of SnPb-2Ag solder with very little grain coarsening. Primary AUSQ and eutectic structures were observed in the high-goldcontent solder joints. Performance differences observed with different components, and the gold content variations, using the two interconnection materials are discussed.
intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2004
Mohammad M. Hossain; Dereje Agonafer; Puligandla Viswanadham; Tommi Reinikainen
Finite element analysis is extensively used for simulating the effect of accelerated temperature cycling in electronic packages. There are number of issues that need to be addressed to improve the current FEM models. One of the limitations for the models presently available is excluding the effect of intermetallic compounds (IMC) (Cu/sub 6/Sn/sub 5/, Cu/sub 3/Sn) formation and growth between solder joint and Cu pad. The mechanical reliability of these IMC clearly influences the mechanical integrity of the interconnection. The brittle failures of solder balls have been identified with the growth of a number of IMC both at the interfaces between metallic layers and in the bulk solder balls. Previous study on intermetallics modeling discussed the energy based approach for predicting the fatigue life. The results show contradictory trends of life, not consistent with experimental data. This paper focuses the fatigue life prediction of the solder joint incorporating the effect of IMC using plastic and creep strain approach in finite element modeling. As a typical application, 3D Quarter model of a CSP is chosen to do the FE analysis. Accelerated temperature cycling is performed to obtain the plastic work due to thermal expansion mismatch between the various materials. Accumulated plastic strains were incorporated to predict the fatigue life. The model incorporates time dependent and time independent plasticity (i.e. creep) for the solder materials. The results are compared with conventional models that do not include intermetallic effects. It is shown that the strain based approach gives results that are consistent with general trends.
2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1 | 2003
Mohammad M. Hossain; Dereje Agonafer; Puligandla Viswanadham; Tommi Reinikainen
The life-prediction modeling of an electronic package requires a sequence of critical assumptions concerning the finite element models. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that constitute the package. Finite element analysis is extensively used for simulating the effect of accelerated temperature cycling on electronic packages. There are a number of issues that need to be addressed to improve the current FEM models. One of the limitations inherent to the presently available models is the accuracy in property values of eutectic 63Sn/37Pb solder or other solder materials (i.e. 62Sn/36Pb/2Ag). Life prediction methodologies for high temperature solders (90Pb/10Sn, 95Pb/5Sn, etc.) or lead-free based inter-connects materials, are almost non-existent due to their low volume use or relative infancy. [1] Another major limitation for the models presently available is excluding the effect of intermetallic compound (Cu6 Sn5 , Cu3 Sn) formation and growth between solder joint and Cu pad due to the reflow processes, rework and during the thermal aging. The mechanical reliability of these intermetallic compounds clearly influences the mechanical integrity of the interconnection. The brittle failures of solder balls have been identified with the growth of a number of intermetallic compounds both at the interfaces between metallic layers and in the bulk solder balls. In this paper, the effect of intermetallic compound in fatigue life prediction using finite element modeling is described. A Chip Scale Package 3D Quarter model is chosen to do the FE analysis. Accelerated temperature cycling is performed to obtain the plastic work due to thermal expansion mismatch between the various materials. Solder joint fatigue life prediction methodologies were incorporated so that finite element simulation results were translated into estimated cycles to failure. The results are compared with conventional models that do not include intermetallic effects. Conventionally available material properties are assumed for the eutectic 63Sn/37Pb solder and the intermetallic material properties. The importance of including intermetallic effect in finite element modeling will be discussed.Copyright
4th International Conference on Adhesive Joining and Coating Technology in Electronics Manufacturing. Proceedings. Presented at Adhesives in Electronics 2000 (Cat. No.00EX431) | 2000
Puligandla Viswanadham
An important aspect in the fabrication of electronic packages and assemblies is the joining of similar as well dissimilar pairs of materials with a range of physicochemical characteristics. Metal-metal, metal-polymer, and polymer-polymer interface are encountered. It is important to ensure adequate interfacial bonding, namely, adhesion strength between the material pairs for product performance in the intended operating environment. In this paper are highlighted some of the adhesion aspects that are relevant to first and second level electronic packaging and their impact on reliability.
Archive | 2001
Puligandla Viswanadham; Tom Chung; Steven O. Dunford
In the last three decades, many innovative microelectronics packaging and interconnection-related technologies, such as tape automated bonding (TAB), flip chip, multi-chip modules (MCMs), and ball grid arrays (BGAs), have been developed, applied, and demonstrated in a variety of electronic products. The demand for high-density, high-performance, high-function, portable consumer electronics continues almost undiminished. The ever-increasing demand for product performance, versatility, and miniaturization, resulted in significant advances in semiconductor device power, performance and pin count. These, in turn, have imposed significant challenges upon electronic companies to provide even more compact, cost-effective, and reliable products [1,2].
Archive | 2004
Puligandla Viswanadham; Steven O. Dunford; Jorma Kivilahti
Archive | 2010
Sridhar Canumalla; Puligandla Viswanadham
Archive | 2007
Sridhar Canumalla; Puligandla Viswanadham