Pulkit Jain

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

A multi-story power delivery technique for 3D integrated circuits

Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some interesting facts and design challenges. A multi-story power delivery technique that can reduce the worst case DC noise by 45% and lower the overhead power consumed in the power supply network by 65% is proposed. A test chip layout in an SOI process, showing a 5.3% area overhead, demonstrates the feasibility of the scheme.

A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor

A truly logic-compatible gain cell eDRAM macro with no boosted supplies is presented. A 2T1C gain cell implemented only with regular thin oxide devices consists of an asymmetric 2T cell and a coupling PMOS capacitor. The PMOS capacitor ensures proper operation even without a boosted supply by utilizing a beneficial coupling for read and a preferential boosting for write. A repair scheme based on a single-ended 7T SRAM has features such as a local differential write and shared control with the main 2T1C array. A storage voltage monitor is proposed to track the retention characteristics of a gain cell eDRAM under PVT variations and to adjust its refresh rate adaptively. A 128 kb eDRAM test chip implemented in a 65 nm Low-Power (LP) process operates at a random access frequency of 714 MHz with a static power dissipation of 161.8 μW per Mb for a 500 μs refresh rate at 1.1 V and 85°C.

A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110µsec

A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110µsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

Thermal and Power Delivery Challenges in 3D ICs

Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks.

A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies

6T SRAMs have been the embedded memory of choice for modern microprocessors due to their logic compatibility, high speed, and refresh-free operation. The relatively large cell size and conflicting requirements for read and write at low operating voltages make aggressive scaling of 6T SRAMs challenging in sub-22nm. Recently, 1T1C embedded DRAMs (eDRAMs) have replaced SRAMs in several server applications reducing the cache area and improving performance [1]. Difficulties in scaling the trench capacitor and the additional process steps involved in manufacturing the thick oxide access devices are currently limiting the wide spread adoption of 1T1C technology. Gain cells have features such as decoupled read and write paths, a nondestructive read, and a 2X higher bit-cell density than a 6T SRAM, making them a strong contender for future embedded memories [2–4]. However, the boosted supplies needed for robust operation necessitates thick oxide devices to prevent gate reliability issues in gain cells. Although this would lead to a larger bit-cell size and decreased macro performance, these limitations have been overlooked in the past. In this paper, we present the following circuit techniques for realizing a truly logic compatible (i.e. thin oxide only implementation) gain cell eDRAM with no boosted supplies; (i) a 2T1C gain cell featuring a beneficial couple-up read and a preferential couple-down write, (ii) a single-ended 7T SRAM to repair weak gain cells, and (iii) a storage voltage monitor capable of tracking PVT and cell retention time for adaptive refresh control. The 64kb test macro in Fig. 28.10.1 achieves a random cycle frequency of 700MHz and a retention time of 500μsec.

Logic-compatible embedded DRAM design for memory intensive low power systems

Circuit techniques for enabling a low power logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes preferential storage node boosting to improve data retention time and increase read margin. A regulated bit-line write scheme is equipped with a steady-state storage node voltage monitor to overcome the data ‘1’ write disturbance problem. An adaptive and die-to-die adjustable read reference bias generator is proposed to cope with PVT variations. Measurement data from 65nm test chips demonstrate a >1.0msec retention time at 0.9V, 85ºC and a <100µW per Mb refresh power at 1.0V, 85ºC which translates into a 50% reduction in static power compared to a power gated SRAM.

An array-based circuit for characterizing latent Plasma-Induced Damage

An array-based Plasma-Induced Damage (PID) characterization circuit with various antenna structures is proposed for efficient collection of massive PID breakdown statistics. The proposed circuit reduces the stress time and test area by a factor proportional to the number of Devices Under Test (DUTs). Measured Weibull statistics from a 12-24 array implemented in 65nm show that DUTs with plate type antennas have a shorter lifetime compared to their fork type counterparts suggesting greater PID effect during the plasma ashing process.

Duty-cycle shift under asymmetric BTI aging: A simple characterization method and its application to SRAM timing

The effect of DC BTI stress on the clock signals duty-cycle has been experimentally verified for the first time based on the precise frequency shift measurement from Ring OSCillators (ROSC). A simple and practical methodology based on the “silicon odometer” beat-frequency detection framework has been proposed for accurately measuring duty-cycle shifts while preventing unwanted BTI recovery. The measurement results from a 65nm test chip were used to further analyze the impact of asymmetric BTI aging during clock gated mode on SRAM timing signals.