C. Kenyon

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers. The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions. Dramatic performance enhancement relative to unstrained devices are reported. These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 1.2nm physical gate oxide and Ni salicide. World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 1.2V are demonstrated. NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region. High NMOS drive currents of 1.26mA//spl mu/m (high VT) and 1.45mA//spl mu/m (low VT) at 1.2V are reported. The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families.

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

A leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by >50%. Aggressive design rules and unlanded contacts offer a 1.0 /spl mu/m/sup 2/ 6-T SRAM cell using 193 nm lithography.

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors

A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported.

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//spl mu/m and 0.5 mA//spl mu/m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA//spl mu/m and 0.6 mA//spl mu/m respectively. Technology design rules allow a 6-T SRAM cell with an area of 2.45 /spl mu/m/sup 2/, while array specific design rule give the densest SRAM reported to date, the 6-T cell has an area of only 2.09 /spl mu/m/sup 2/. Excellent yield and performance is demonstrated on a 18 Mbit CMOS SRAM.

100 nm gate length high performance/low power CMOS transistor structure

We report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V. These transistors are incorporated in a 180 nm logic technology generation. Various process enhancements are incorporated to significantly improve transistor current drive capability relative to the results published by Yang et al. (1998). Unique transistor features responsible for achieving high performance are described. NMOS and PMOS devices demonstrate drive current of 1.04 mA//spl mu/m and 0.46 mA//spl mu/m respectively at 1.5 V and 3 nA//spl mu/m I/sub OFF/. These are the best drive currents reported to date at fixed I/sub OFF/. They represents 10% drive current improvement for both NMOS and PMOS devices relative to the results published by Yang without any change in gate-oxide thickness. High performance is demonstrated down to 1.2 V. Inverter delay of less than 10 psec is reported at 1.5 V at very moderate I/sub OFF/ values.

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance operation from 0.7 to 1.4 V, and a 5% linear shrink to reduce the 6-T SRAM cell to 2.00 /spl mu/m/sup 2/ while still using 248 nm lithography. Saturation drive currents of 1.30 mA//spl mu/m for N-channel and 0.66 mA//spl mu/m for P-channel low VT devices are the highest reported to date. Excellent device short channel effects are obtained for the 60 nm gate length devices as measured by the 270 mV threshold voltage and <100 mV/V DIBL. These results have been achieved on both 200 and 300 mm wafers.