Qamar Wahab

Liquid phase epitaxial growth of SiC

The characteristics of 4H and 6H-SiC epitaxial growth from the liquid phase by using a sandwich configuration are presented. The preparation procedure of the two-component solvent and the growth technique are described. Growth rates exceeding 300 lm/h have been obtained. The transport of solute is a⁄ected by formation of complexes within the liquid zone which decrease the growth rate. The growth rate depends mainly on the temperature gradient but is also influenced by the solvent composition. Important growth parameters such as temperature gradient and substrate o⁄-orientation have a profound influence on the morphological stability. It is shown that if these are not properly chosen, constitutional supercooling may appear. The polytype of the substrate is reproduced in the grown material and the structural quality is good. Common defects are discussed. ( 1999 Elsevier Science B.V. All rights reserved.

High temperature CVD growth of SiC

Two high temperature CVD techniques, respectively optimised for epitaxial and crystal growth, are presented. A chimney reactor has been developed for fast epitaxy, carried out at 1700‐1900°C, with growth rates ranging from 10 to 25 m mh 1 , and a material quality close to conventional CVD processes. The growth of 4H-SiC epilayers with low n-type doping (10 14 ‐10 15 cm 3 ) and carrier lifetimes up to 0.4 ms is described, while the feasibility of high voltage Schottky rectifiers (1.8 kV) is demonstrated. On the other side, developments of the stagnant flow HTCVD process, where growth is carried out at 2000‐2300°C, are shown to enable growth rates ranging from 0.3 up to 0.8 mm h 1 . The main characteristics of HTCVD grown SiC crystals (up to nearly 7 mm thick) are described.

Interfacial void formation during vapor phase growth of 3C-SiC on Si(0 0 1) and Si(1 1 1) substrates. Characterization by transmission electron microscopy

The formation and microstructure of voids at the interface between epitaxial films of 3C-SiC on Si(0 0 1) and Si(1 1 1) substrates have been investigated using cross-sectional transmission electron microscopy. SiC films were deposited using three different techniques; atmospheric pressure chemical vapor deposition (APCVD) in a hot-wall type reactor using the silane-propane-hydrogen system in a substrate temperature (Ts) regime 900°C to 1300°C, reactive magnetron sputtering of Si target in mixed CH4Ar discharge at Ts = 850°C, and sequential sputtering from Si and C (graphite) targets in pure Ar discharge at Ts between 710°C and 850°C. Voids formed in the Si substrates with primary faceting on {1 1 1} planes and increased in size with increasing temperature. Truncation of voids was on {0 0 1} and {1 1 3} planes as expected from shape equilibrium, but also truncation on apparent {0 1 1} facets were observed between inclined {1 1 1} planes as an effect of growth kinetics. The presence of voids resulted in an inhomogeneous residual strain state in the films during cooling from the deposition temperature due to thermal mismatch to the substrate as evidenced by a significant broadening of the SiC(0 0 2) peak in X-ray diffraction. Corresponding strain relaxation of the SiC film in the absence of voids resulted in plastic deformation of the Si substrate.

Designing, Fabrication and Characterization of Power Amplifiers Based on 10-Watt SiC MESFET & GaN HEMT at Microwave Frequencies

This paper describes the design, fabrication and measurement of two single-stage class-AB power amplifiers covering the frequency band from 0.7-1.8 GHz using a SiC MESFET and a GaN HEMT. The measured maximum output power for the SiC amplifier at Vd = 48 V was 41.3 dBm (~13.7 W), with a PAE of 32% and a power gain above 10 dB. At a drain bias of Vd= 66 V at 700 MHz the Pmax was 42.2 dBm (~16.6 W) with a PAE of 34.4%. The measured results for GaN amplifier are; maximum output power at Vd = 48 V is 40 dBm (~10 W), with a PAE of 34% and a power gain above 10 dB. The results for SiC amplifier are better than for GaN amplifier for the same 10-W transistor.

Single-stage, high efficiency, 26-watt power amplifier using SiC LE-MESFET

This paper describes a single-stage 26 W negative feedback power amplifier, covering the frequency range 200-500 MHz using a 6 mm gate width SiC lateral epitaxy MESFET. Typical results at 50 V drain bias for the whole band are, around 22 dB power gain, around 43 dBm output power, minimum power added efficiency at P1 dB is 47% at 200 MHz and maximum 60% at 500 MHz and the IMD3 level at 10 dB back-off from P1 dB is below -45 dBc. The results at 60 V drain bias at 500 MHz are, 24.9 dB power gain, 44.15 dBm output power (26 W) and 66% PAE.

Purity and surface structure of thick 6H and 4H SiC layers grown by sublimation epitaxy

Thick epitaxial layers have been grown with high growth rates by sublimation epitaxy. The appearance of steps on the as-grown surfaces have been investigated on both 6H and 4H SiC for both the (0001) and (0001) faces. On the Si-face the surface structure for 6H and 4H SiC shows a similar appearance whereas on the C-face a slight difference in the appearance of the steps is observed as compared with the Si-face. The incorporation of impurities depending on growth parameters has been studied. High resistivity layers with smooth morphology have been grown without intentional doping. This shows that sublimation epitaxy is a suitable technique for growth of semi-insulating material with a high growth rate.

Flexible Power Amplifiers Designing from Device to Circuit Level by Computational Load-Pull Simulation Technique in TCAD

The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.

The limiting frontiers of maximum DC voltage at the drain of SiC microwave power transistors in case of class-A power amplifier

In this paper, we have studied the limiting frontiers of maximum DC voltage, which can be applied at the drain of SiC MESFET in case of class-A power amplifier. In this technique a DC bias and RF input signal to the gate while a DC bias and RF output signal simultaneously was applied to the drain terminal. The RF source at the drain delivered a sine wave at the fundamental frequency thereby acting as a short at the higher harmonic frequencies. These signals thus also acted as an active match to the transistor. The results from the time domain simulations were then transformed into frequency domain using FFT in MATLAB.

A non-linear TCAD large signal model to enhance the linearity of transistor

In this paper, the proposed technique can be used to study the internal device non-linearity by TCAD device level simulations to enhance the device performance by physical structure/doping.A new large signal simulation technique to study non-linear effects of microwave power transistor