Qiaoyan Yu

Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip

High-end MPSoC systems with built-in high-radix topologies achieve good performance because of the improved connectivity and the reduced network diameter. In high-end MPSoC systems, fault tolerance support is becoming a compulsory feature. In this work, we propose a combined method to address permanent and transient link and router failures in those systems. The LBDRhr mechanism is proposed to tolerate permanent link failures in some popular high-radix topologies. The increased router complexity may lead to more transient router errors than routers using simple XY routing algorithm. We exploit the inherent information redundancy (IIR) in LBDRhr logic to manage transient errors in the network routers. Thorough analyses are provided to discover the appropriate internal nodes and the forbidden signal patterns for transient error detection. Simulation results show that LBDRhr logic can tolerate all of the permanent failure combinations of long-range links and 80% of links failures at short-range links. Case studies show that the error detection method based on the new IIR extraction method reduces the power consumption and the residual error rate by 33% and up to two orders of magnitude, respectively, compared to triple modular redundancy. The impact of network topologies on the efficiency of the detection mechanism has been examined in this work, as well.

Assessing CPA resistance of AES with different fault tolerance mechanisms

Countermeasures for Advanced Encryption Standard (AES) to thwart side-channel attack and fault attack are typically investigated in a separate fashion. There is lack of thorough investigation on how one countermeasure specifically for one attack affects the efficiency of another attack. In this work, we consider three different fault detection (FD) methods - double modular redundancy (DMR), inverse function (inverse), and even parity check code (parity). We perform FPGA-based systematic analysis to investigate the impact of FD schemes on the correlation power analysis (CPA) resistance of a complete AES implementation. Moreover, the power model used in the existing work is Hamming weight rather than the powerful Hamming distance one. Our experimental results show that, in some scenarios, the use of fault detection mechanisms in AES improves the resistance against CPA. For instance, applying a parity FD to the AESs S-Box makes it harder to retrieve the key than the case without any FD protection.

Fine-grained splitting methods to address permanent errors in Network-on-Chip links

We propose a series of fine-grained splitting transmission methods to address permanent errors in Network-on-Chip (NoC) links, maintaining high throughput and ensuring reliability. While prior permanent error management approaches discard the entire or half link, our proposed methods greatly improve wire utilization in the presence of permanent errors. A case study shows that our methods achieve throughput improvement of 234% and 56%, respectively, compared to fault-tolerant routing and half-splitting methods in the presence of high number of permanent errors.

Addressing network-on-chip router transient errors with inherent information redundancy

We exploit the inherent information redundancy in the control path of Network-on-Chip (NoC) routers to manage transient errors, preventing packet loss and misrouting. Outputs of the routing arbitration units in NoC routers can be used to determine arbitration failures, because the valid arbitration outputs are a subset of all possible values. This feature is exploited to detect and correct logic and register errors in the router arbitration control path. The proposed method is complementary to other error management methods for NoC routers. An analytical reliability model of our method is provided, including parameters such as logic unit size, different error rates for logic gates and registers, and the location of faulty elements. Compared to triple-modular redundancy (TMR), the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total area and power by 43% and 64%, respectively. In the presented case studies, two traffic traces from the PARSEC benchmark suite are used to evaluate the average latency and energy consumption. Simulations performed on a 4× 4 NoC show that our method reduces the average latency by up to 50% and reduces average energy by up to 70% compared to other methods.

Hardware security assurance in emerging IoT applications

The Internet of Things (IoT) offers a more advanced service than a single device or an isolated system, as IoT connects diverse components, such as sensors, actuators, and embedded devices through the internet. As predicted by Cisco, there will be 50 billion IoT connected devices by 2020. Integration of such a tremendous number of devices into IoT potentially brings in a new concern, system security. In this work, we review two typical hardware attacks that can harm the emerging IoT applications. As IoT devices typically have limited computation power and need to be energy efficient, sophisticated cryptographic algorithms and authentication protocols are not suitable for every IoT device. To simultaneously thwart hardware Trojan and side-channel analysis attacks, we propose a low-cost dynamic permutation method for IoT devices. Experimental results show that the proposed method achieves 5.8X higher accumulated partial guessing entropy than the baseline, thus strengthening the IoT processing unit against hardware attacks.

A hardened network-on-chip design using runtime hardware Trojan mitigation methods

Due to the globalized semiconductor business model, malicious hardware modifications, known as hardware Trojans (HTs), have risen up as a big concern for chip security. HT detection and mitigation methods for general integrated circuits have been investigated in the past decade. However, the majority of the existing efforts are not customized for HTs in Networks-on-Chip (NoCs). To complement the firmware and software level methods for rogue NoCs detection, we propose countermeasures to harden the NoC hardware design against tampering. More specifically, we propose a collaborative dynamic permutation and flit integrity check method to mitigate the potential inside-router HTs inserted by the disloyal member in the NoC design house or the 3rd-party system integration company. Our method improves the number of received packets by up to 70.1% over the other methods if the HT controls the NoC packet destination address. The average link availability of our method is 43.7% higher than that of the exiting methods. Our method increases the effective average latency by up to 63.4%, 68.2%, and 98.9% for the single HT in the destination, header, and tail fields, respectively, over the existing methods. We propose countermeasures to harden the NoC design, rather than fully relying on software or firmware solutions to detect a compromised NoC used in the MPSoC.Our router-level HT mitigation mechanism raises the bar for an adversary to simultaneously control multiple routing hops to create a malicious communication path between two IP cores in the NoC-based MPSoC.The proposed collaborative dynamic permutation and flit integrity check method is capable of examining the invariables of NoC to immediately terminate the detected HTs.

Fault-tolerant methods for a new lightweight cipher SIMON

We propose three fault-tolerant methods for a new lightweight block cipher SIMON, which has the potential to be a hardware-efficient security primitive for embedded systems. As a single fault in the encryption (decryption) process can completely change the ciphertext (received plaintext), it is critical to ensure the reliability of encryption and decryption modules. We explore double-modular redundancy (DMR), reverse function, and a parity check code combined with a non-linear compensation function (EPC) to detect faults in SIMON. The proposed fault-tolerant methods were implemented in iterative and pipelined SIMON architectures. The corresponding hardware cost, power consumption, and fault detection failure rate were assessed. Simulation results show that EPC-SIMON consumes less area and power than DMR-SIMON and Reversed-SIMON but yields a higher fault detection failure rate as the number of concurrent faults increases. Moreover, our experiments show that the impact of fault location on the fault-detection failure rates for different methods is not consistent.

Strengthening SIMON Implementation Against Intelligent Fault Attacks

Driven by malicious intent, attackers are impelled to extract the cipher key and thus compromise the cryptosystem through fault attacks. Existing fault-detection methods can effectively detect random faults in the cipher implementation, but yield a high fault bypass rate (FBR) under intelligent fault attacks. To address this limitation, we propose a new microarchitecture to thwart fault attacks that place mathematically symmetric faults on the two encryption data paths. To further reduce the FBR for a new lightweight cipher SIMON, we propose a new countermeasure that integrates operand permutation and masking techniques. Closed-form expressions for depermutation and demasking in SIMON are provided in this letter. Our method was assessed under two fault attack scenarios (random and symmetric fault injections) with bit-flip, stuck-at-0, and stuck-at-1 fault models. Simulation results show that our method minimizes the FBR to zero with the fault attack scenarios of symmetric fault location and stuck-at-0 fault injections. Overall, the proposed method outperforms the existing fault-detection methods in multiple fault attack conditions, at the cost of 5% more area overhead than the most hardware-efficient fault detection method.

A novel signaling technique for high-speed wireline backplane transceiver: Four phase-shifted sinusoid symbol (PSS-4)

This paper proposes a novel four phase-shifted sinusoid symbol (PSS-4) signaling technique to relief high-speed wireline backplane transceiver to reduce large intersymbol interference. The four-level pulse amplitude modulation (PAM-4) and other existing amplitude modulation techniques have been widely used to simplify transceiver equalization design for highly dispersive channels. Unfortunately, PAM-4 and other methods reduce the symbol rate at the expense of signal-to-noise ratio (SNR) and thus limit the bit-error-rate (BER). The proposed PSS-4 signaling avoids large SNR degradation by using four phase-shifted symbols to transmit two-bit data. The experimental results show that with sufficient equalization, our PSS-4 signaling can achieve over 2 dB larger SNR than the conventional non-return-to-zero (NRZ), Duobinary, and PAM-4 signaling techniques. In addition, for a target BER of 1E-12, the proposed PSS-4 signaling has the largest sampling range comparing against existing backplane signaling techniques. Furthermore, compared with NRZ-based backplane transceiver, PSS-4 signaling reduces the equalizer power consumption by 24%.

Transient error management for partially adaptive router in network-on-chip (NoC)

We propose a concatenate error detection method that exploits inherent information redundancy in network-on-chip (NoC) router, to address transient route computation errors. In our previous works, inherent information redundancy has been successfully employed to management transient errors in routers using XY deterministic routing algorithm. To prevent misrouting caused by transient errors injected in the partially adaptive router, we improve our previous method by using concatenate error detection logic. The proposed method is applied to a recent partially adaptive router based on logic-based distributed routing (LBDR). Analysis and simulation results show that the proposed method reduces the residual error rate by up to 1.98× and 3.47× over our previous approach and triple modular redundancy (TMR), respectively. More importantly, the proposed method consumes 2.6× less area and 2.1× less power consumption compared to TMR.