Paul Ampadu

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT and SSD) is integrated individually into the noninterrupting adaptive system, and a case study is performed to compare them with Hamming and Bose-Chaudhuri-Hocquenghem (BCH) code implementations. In the presence of permanent errors, the probability of correct transmission in the proposed systems is improved by up to 140% over the standalone Hamming code. Furthermore, our methods achieve up to 38% area, 64% energy, and 61% latency improvements over the BCH implementation at comparable error performance.

On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects

We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their impact on the number of wires in the link, codec delay, reliability, and energy consumption. Analytical models are presented to estimate codec delay and residual flit error rate. The analyses are validated by comparison with simulation results. In a case study using H.264 video encoder in a network-on-chip environment, the method of combining Hamming product codes with type-II HARQ achieves several orders of magnitude improvement in residual flit error rate. For a given residual flit error rate requirement (e.g., 10-20), this method yields up to 50% energy improvement over other error control methods in high-noise conditions.

Managing Temperature Effects in Nanoscale Adaptive Systems

This book discusses new techniques for detecting, controlling, and exploiting the impacts of temperature variations on nanoscale circuits and systems. A new sensor system is described that can determine the temperature dependence as well as the operating temperature to improve system reliability. A new method is presented to control a circuit’s temperature dependence by individually tuning pull-up and pull-down networks to their temperature-insensitive operating points. This method extends the range of supply voltages that can be made temperatureinsensitive, achieving insensitivity at nominal voltage for the first time.

Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment

We present an adaptive error control method for switch-to-switch links in a variable noise environment, to meet reliability requirements and achieve energy-efficiency. Unlike worst-case error correction coding (ECC), the proposed method is capable of selecting the most effective ECC scheme based on predicted link quality at runtime. Our method configures the ECC codec to obtain the desired error correction strength using a set of single-error correction (SEC) codes combined with interleaving. The method can effectively handle multi-cycle and adjacent multi-wire errors existing on switch-to-switch links. An experimental case study shows that the adaptive method can increase the energy-efficiency by up to 19% over a fixed ECC scheme, for a given residual flit error rate. Furthermore, energy reduction affected by different multi-wire and multi-cycle noise scenarios are compared.

Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip

We propose a transient and permanent error co-management method for NoC links to achieve low latency, high throughput and high reliability, while maintaining energy efficiency. To reduce the energy overhead, a configurable error control coding adapts the number of redundant wires to the varying noise conditions, achieving different error detection capability. Infrequently used redundant wires are used as spare wires to replace broken links. Furthermore, a packet rebuilding/restoring algorithm that cooperates with a shortened error control coding method is proposed to support a low-latency splitting transmission. With this co-management method, we manage transient errors and a small number of permanent errors, without using extra spare wires, to reduce the need for adaptive routing. Simulation results show that the proposed method achieves up to 71% packet latency reduction and 20% throughput improvement, compared to previous methods. Case studies show that our method reduces the energy per packet by up to 68% and 48% for low and high permanent error conditions, respectively.

Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration

We exploit the inherent information redundancy in the control path of Networks-on-Chip (NoCs) routers to manage transient errors, preventing packet loss and misrouting. Unlike fault-tolerant routing, our method does not drop packets when faults occur in routers and thus does not increase the burden on neighboring routers. Unlike the NoC interconnect links, the routing operation is nonlinear and standard error control coding methods cannot be used. Instead, our method exploits existing information redundancy in the router, significantly reducing the area overhead and power consumption compared to triple-modular redundancy (TMR). An analytical reliability model of our method is provided, including parameters such as circuit size, different error rates for logic gates and registers, and the location of a faulty element. Compared to TMR, the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total power and area by 43% and 64%, respectively. Simulations performed on a 4×4 NoC show that our method reduces the average latency by up to 90% and 12% over no-protection and TMR methods, respectively.

A Flexible Parallel Simulator for Networks-on-Chip With Error Control

This paper presents a flexible parallel simulator to evaluate the impact of different error control methods on the performance and energy consumption of networks-on-chip (NoCs). Various error control schemes can be inserted into the simulator in a plug-and-play manner for evaluation. Moreover, a highly tunable fault injection feature is developed for modeling various fault injection scenarios, including different fault injection rates, fault types, fault injection locations, and faulty flit types. Case studies performed in the proposed flexible simulation environment are presented to demonstrate the impact of a set of error control schemes on NoC performance and energy in different noise scenarios. This paper also uses the simulator to provide design guidelines for NoCs with error control capabilities.

A Study of Geometry Effects on the Performance of Ballistic Deflection Transistor

We present the results of an experimental study of dimensional ratios dependencies on the performance of a ballistic deflection transistor (BDT) operating in a quasi-ballistic regime. Experimental transconductance change based on geometry variations is studied for smaller and larger devices with channel width of 300 and 500 nm, respectively. Transconductance variation for a series of drain biases is also observed for a specific geometry and dimension. By means of Monte Carlo modeling we report the effect of different geometry parameters on the transfer characteristics of BDTs. The strength of the gate control in the InGaAs channel is analyzed.

Adaptive error control for nanometer scale network-on-chip links

The authors present an adaptive error control method for switch-to-switch links in nanoscale networks-on-chip to manage reliability, throughput and energy. Unlike previous works, the proposed method adjusts both error detection and correction simultaneously at runtime. For a given application or predicted noise scenario, an appropriate error control scheme is selected for reliable message transmission. When link conditions degrade, more powerful error detection and correction are temporarily provided to recover the previous message. To achieve this adaptation, the authors create a configurable M-error correction, 2M-error detection code, combined with a hybrid automatic repeat request retransmission policy. Simulation results show that the proposed method can reduce residual flit error rate by over three orders of magnitude and achieve up to 75% higher average throughput compared to other error control methods. Further, average energy per successfully transmitted flit is reduced by up to 15% compared to fixed error control in a 65-nm technology. Compared to a recent adaptive error detection method, a 34% energy reduction can be achieved in high noise environment, at the expense of moderate area overhead.

Temperature Effects in Semiconductors

The changes in temperature described in the previous chapter affect the speed, power, and reliability of our systems. Throughout this book, we will examine all three of these metrics, though the majority of our discussion will be on how temperature affects the speed performance. In this chapter, we discuss the problem of temperature variation at the device and circuit level. In Sect. 2.1, we provide a background on the material dependences on temperature. In Sect. 2.2, the normal and reverse temperature dependence regimes are described. In Sect. 2.3, we explore how these dependences change with technology scaling and the introduction of new processing materials, such as high-κ dielectrics and metal gates.