Qilong Bao

Normally OFF GaN-on-Si MIS-HEMTs Fabricated With LPCVD-SiN x Passivation and High-Temperature Gate Recess

Low-current-collapse normally OFF GaN-on-Si MIS high-electron-mobility transistors (MIS-HEMTs) are fabricated with low-pressure chemical-vapor-deposited SiN_x (LPCVD-SiN_x) passivation and high-temperature low-damage gate-recess technique. The high-thermal-stability LPCVD-SiN_x enables a passivation-prior-to-ohmic process strategy and effectively suppresses deep states at the passivation/HEMT interface. The fabricated MIS-HEMTs feature a high V_TH of +0.85 V at the drain current of 1 μA/mm and a remarkable ON/OFF current ratio of 10¹⁰ while reduced dynamic ON-resistance as compared to plasma-enhanced chemical-vapor-deposited SiO₂ passivation. High field-effect channel mobility of 180 cm²/V·s is achieved, leading to a high maximum drain current density of 663 mA/mm.

Mechanism of Ti/Al/Ti/W Au-free ohmic contacts to AlGaN/GaN heterostructures via pre-ohmic recess etching and low temperature annealing

The physical mechanism of low-thermal-budget Au-free ohmic contacts to AlGaN/GaN heterostructures is systematically investigated with current-voltage, high-resolution transmission electron microscopy, and temperature-dependent contact resistivity characterizations. With a low annealing temperature of 600 °C, pre-ohmic recess etching of the AlGaN barrier down to several nanometers is demonstrated to be an effective method to reduce the contact resistance between Ti/Al/Ti/W ohmic metals and AlGaN/GaN heterostructures. However, further over recess of the AlGaN barrier leads to only sidewall contact to 2D electron gas channel and thus degraded contact performance. It is verified by temperature-dependent contact resistivity measurements that field emission (tunneling) dominates the current transport mechanism in Au-free ohmic contacts with AlGaN barrier partially and over recessed, while both field emission and thermionic emission contribute to traditional Ti/Al/Ni/Au ohmic contacts to AlGaN/GaN heterostructur...

Investigation of the interface between LPCVD-SiNx gate dielectric and III-nitride for AlGaN/GaN MIS-HEMTs

The interface between silicon nitride (SiNx) gate dielectric grown by low pressure chemical vapor deposition (LPCVD) and III-nitride heterostructure is investigated by a systematical comparison of AlGaN/GaN high-electron-mobility transistors (HEMTs) and metal-insulator-semiconductor HEMTs (MIS-HEMTs). A 20-nm LPCVD-SiNx grown at 650 °C features a high breakdown E-field of 13 MV/cm and a large conduction-band offset of 2.75 eV to GaN. High ON/OFF current ratio (∼1010) as well as breakdown voltage (∼878 V) is realized by employing the LPCVD-SiNx layer as both the gate and passivation dielectrics. Most important of all, about 2.6 × 1013 cm−2 positive fixed charges are confirmed to be present at the LPCVD-SiNx/III-nitride interface, as revealed by pulsed transfer characterizations and energy-band simulations. The trap density at LPCVD-SiNx/III-nitride interface is also experimentally determined.

Effect of interface and bulk traps on the C–V characterization of a LPCVD-SiNx/AlGaN/GaN metal-insulator-semiconductor structure

Silicon nitride (SiNx) film grown by low-pressure chemical vapor deposition (LPCVD) is utilized as a gate dielectric for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Trap distribution at the gate-dielectric/III-nitrides interface is characterized by a temperature-dependent ac-capacitance technique. The extracted interface state density D it decreases from 2.92 × 1013 to 1.59 × 1012 cm−2 eV−1 as the energy level depth (E C-E T) increases from 0.29 to 0.50 eV, and then levels off to E C-E T = 0.80 eV. Capacitance-mode deep level transient spectroscopy (C-DLTS) and energy band diagram simulations reveal that deep levels with E C-E T > 0. 83 eV are responsible for the dispersion of capacitances at high temperature (>125 °C) and low frequencies (<1 kHz). A high-resolution transmission electron microscope (TEM) reveals that re-oxidation of the RCA-treated AlGaN barrier surface may be responsible for the relatively high density of shallow states at the LPCVD-SiNx/III-nitride interface.

High-performance fully-recessed enhancement-mode GaN MIS-FETs with crystalline oxide interlayer

In this work, we developed an effective technique to form a sharp and stable crystalline oxidation interlayer (COIL) between the reliable LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The COIL was formed using oxygen-plasma treatment, followed by in-situ annealing prior to the LPCVD-SiNx deposition. The COIL plays the critical role of protecting the etched GaN surface from degradation during high-temperature (i.e. at ∼ 780 °C) process, which is essential for fabricating enhancement-mode GaN MIS-FETs with highly reliable LPCVD-SiNx gate dielectric and fully recessed gate structure. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a Vth of 1.15 V, small on resistance, thermally stable Vth and low positive-bias temperature instability (PBIT).

High Uniformity Normally-OFF GaN MIS-HEMTs Fabricated on Ultra-Thin-Barrier AlGaN/GaN Heterostructure

Ultra-thin-barrier (UTB) AlGaN/GaN heterostructure is utilized for fabrication of normally-OFF GaN metal- insulator-semiconductor high-electron-mobility transistors (MISHEMTs). The sheet resistance of 2-D electron gas in the UTB Al_0.22Ga_0.78N(5-nm)/GaN heterostructure is effectively reduced by SiN_x passivation grown by low-pressure chemical vapor deposition, from 2570 to 334 Q/D. The fabricated Al₂O₃/AlGaN/GaN MIS-HEMTs exhibit normally-OFF behavior with good V_TH uniformity and low VTH-hysteresis. 20 mm-gate-width power devices featuring a low R_on of 0.75 Ω (I_D,MAX = 6.5 A) are also demonstrated on the platform.

Evolution of traps in TiN/O3-sourced Al2O3/GaN gate structures with thermal annealing temperature

The interface between a GaN epitaxial layer and an Al2O3 gate dielectric, which was grown by atomic layer deposition using O3 as the oxygen source on top of a 2-nm H2O-sourced Al2O3 interfacial layer, was engineered by applying a high-temperature postmetal annealing (PMA) process. The O3-sourced Al2O3 gate dielectric featured good thermal stability and breakdown behavior, even at a PMA temperature of 700 °C. Moreover, deep interface/bulk traps in the O3-sourced Al2O3/GaN structures were effectively suppressed, as confirmed by characterization using deep-level transient spectroscopy. However, extended line defects and holelike traps were observed at higher PMA temperatures (750 °C), which were considered to originate from the interface reaction between partially crystallized O3-sourced Al2O3 and the GaN epitaxial layer.