Qingjin Du

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is reported in this brief. A new switching control scheme is employed in the circuit to enable the capability of locking to frequencies either above or below the start-up frequency without initialization. To reduce the spurious output power level, a low-bandwidth auxiliary loop [period error compensation loop (PECL)] is employed to compensate for the output period error caused by the phase realignment errors. This frequency multiplier is implemented in TSMC 0.18-mum CMOS technology and measured with a synthesized frequency source. A significant reduction of the output spurs from -23 to -46.5 dB at 1.216 GHz is achieved by enabling the PECL. The measured cycle-to-cycle timing jitter at 2.16 GHz is 1.6 ps (rms) and 12.9 ps (pk-pk), and the phase noise is -110 dBc/Hz at 100-kHz offset with a power consumption of 19.8 mW at a 1.8-V power supply

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

A 4 GHz ADPLL-based integer-N frequency synthesizer is reported in this paper. It employs a low-complexity digital phase and frequency detector as well as a non-linear phase and frequency decision circuit to significantly reduce the hardware complexity while maintain a comparable in-lock performance to other high-complexity ADPLLs. The ADPLL was fabricated in 90 nm CMOS technology to prove its feasibility. Operating with a high-frequency-resolution DCO, the proposed low-complexity ADPLL exhibits a programmable loop bandwidth from 100 kHz to 6 MHz with and an excellent in-band phase noise performance.

A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution

This paper reports a LC-based digitally controlled oscillator (DCO) with an enhanced frequency resolution and an extended linear frequency tuning range. It has a center frequency of 3.3 GHz. and a frequency tuning range of 600 MHz covered by 64 different frequency bands. Each frequency band has 2048 linear tuning levels with a frequency step of 5 kHz. This DCO was implemented in 90 nm CMOS and the measured frequency tuning characteristics arc provided in this paper. The DCO exhibits a phase noise of -11 NdBc/Hz. at 1 MHz frequency offset. The DCO core consumes 2 mA current from 1.2 V supply.

Event-Driven Modeling and Simulation of an Digital PLL

An event-driven modeling and simulation technique, implemented in Matlab is presented in this paper. It enables rapid and accurate simulation as it only calculates the time instants of interest. This technique is successfully applied to behavioral modeling and simulation of a digital phase-locked loop. The simulation environment retains the flexibility of modeling and mathematical manipulation that characterizes Matlab. For example, it allows time-domain modeling phase noise of each component of a digital PLL

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur

This paper presents a new programmable delay-locked loop based frequency multiplier with a period error compensation loop (PECL) designed to reduce the output spurious power level. The low bandwidth auxiliary PECL compensates the output period error caused by the in-lock errors from various noise sources. By employing a novel switching control scheme, the circuit is capable of locking to frequencies either above or below the start up frequency without initialization. Programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 900 MHz to 2.9 GHz. The circuit is implemented in TSMC 0.18mum CMOS technology and measured with the reference signal from an RF signal generator. A 23 dB spur reduction from -23dB to -46.5dB at 1.216GHz is observed from the measurement results. The measured cycle-to-cycle timing jitter at 2.16GHz is 1.6ps (rms) and 12.9 ps (pk-pk), and the measured phase noise is -110 dBc/Hz at 100 kHz offset with a power consumption of 19.8 mW at a 1.8 V supply

A 2.5 Gb/s, Low Power Clock and Data Recovery Circuit

This paper presents an all-digital clock and data recovery circuit with the data bit rate of 2 to 5Gb/s. With the eye-tracking technique instead of the traditional data edge tracking method, the jitter tolerance is increased by keeping the sampling clock away from the jitter distribution region confirmed by Matlab simulation. A bang-bang PD with a phase distance of 1/4 UI is chosen, and a jitter tolerance of 0.75UI is achieved. A CMOS circuit was implemented in CMOS 90 nm technology with low complexity. The circuit consumes a power of 9 mW at 2.5 Gbps at a 1.2 v supply.

A delay-locked frequency synthesizer with low phase noise performance

This paper presents a delay-locked frequency synthesizer implemented in 0.18 /spl mu/m CMOS technology. Symmetrical structures were employed in the circuit to reduce the inter-period jitter and phase noise. With the reference signal from an RF generator, the measured phase noise performance is of -105.5 dBc/Hz at 10 kHz offset with the carrier frequency of 2.07 GHz.

An eye detection technique for clock and data recovery applications

An eye detection technique to detect maximum vertical eye opening points for data recovery circuit (CDR) applications and the circuit implementation of an eye detector (ED) are reported in this paper. The ED samples the incoming data to generate the retimed data and produces an error signal indicating whether the sampling point leads or lags the maximum eye opening point, where the lowest BER is expected. The ED is implemented in CMOS 0.18mum technology, and its feasibility is confirmed by transistor-level simulations

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider

A delay-locked loop based clock generator with the multiplication ratios from 13 to 20 using a programmable dynamic frequency divider is presented in this paper. Compared with the conventional dividers, a dynamic frequency divider achieves both low transistor count and low power consumption. This design employs re-circulating DLL structure to remove the phase noise accumulated within each reference period, and avoid the effect of the mismatch among delay stages to improve the output jitter performance. Implemented in 0.18 mum CMOS technology, this design operates up to 2.9 GHz. With a reference signal from an RF signal generator, the measured phase noise for the carrier frequency of 2.795 GHz is -110 dBc/Hz at 100 KHz offset, and the RMS timing jitter at 2 GHz is 3.68 pS. The circuit consumes approximately 19 mW at 2 GHz output and occupies an area of less than 0.06 mm2

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System

This paper presents a jitter reduction technique utilized in a cyclic injection DLL clock generator to improve the output timing jitter performance for data communication systems. An auxiliary loop with a period error detector finely tunes the VCDL delay value to minimize the period variations. Programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 0.9 GHz to 2.9 GHz. The circuit is implemented in 0.18 mum CMOS technology and a significant cycle- to-cycle timing jitter reduction from 21 ps to 2.5 ps at 2.9 GHz is obtained from the measured results when the jitter reduction technique is enabled. The measured phase noise is -119.6 dBc/Hz at 100 kHz offset with the carrier frequency of 2.795 GHz.