Tad Kwasniewski

Delta-sigma modulation in fractional-N frequency synthesis

A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Delta - Sigma modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques. >

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCOs implemented in 1.2-/spl mu/m CMOS technology confirm with the simulation predictions. The prototype VCOs exhibits 926-MHz operation with -83 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption.

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is reported in this brief. A new switching control scheme is employed in the circuit to enable the capability of locking to frequencies either above or below the start-up frequency without initialization. To reduce the spurious output power level, a low-bandwidth auxiliary loop [period error compensation loop (PECL)] is employed to compensate for the output period error caused by the phase realignment errors. This frequency multiplier is implemented in TSMC 0.18-mum CMOS technology and measured with a synthesized frequency source. A significant reduction of the output spurs from -23 to -46.5 dB at 1.216 GHz is achieved by enabling the PECL. The measured cycle-to-cycle timing jitter at 2.16 GHz is 1.6 ps (rms) and 12.9 ps (pk-pk), and the phase noise is -110 dBc/Hz at 100-kHz offset with a power consumption of 19.8 mW at a 1.8-V power supply

A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops

This paper presents a general ring oscillator circuit topology for high speed operation, multiphase output and wide range tuning. The topology uses sub-feedback inverters to construct a fast loop for long chain ring oscillator to achieve high speed. The operating frequency of the ring oscillator is directly proportional to the transconductance (G/sub m/) of sub-feedback inverters which can be controlled with an external voltage. Both single-ended and differential controlled voltage and inverter stages can be used. A quadrature output ring oscillator based on three-stage sub-feedback loops is designed and fabricated in a 0.5 /spl mu/m CMOS process for a 1.25 GHz clock recovery application. The circuit operates from 400 MHz up to 2 GHz, and consumes 3 mW at 1.25 GHz with 3.3 V power supply.

Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis

This paper presents the design consideration of high order digital /spl Delta//spl Sigma/ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (MASH 1-2) is designed and implemented which allows for the input to operate over 75% of the input adder capacity. The number of the output levels is reduced to two bits. The circuit was verified through simulation, ASIC implementation and exhibits high potential for a gigahertz range, low-power monolithic CMOS frequency synthesizer.

A chip set for pipeline and parallel pipeline FFT architectures

A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2N point, pipeline FFTs. Both devices have been fabricated in 1.5μm CMOS gate array technology.

Configurable K-best MIMO detector architecture

In MIMO communication systems, K-best decoding algorithm achieves near optimal performance with reduced complexity. Simulation results show that a configurable MIMO detector can improve system performance over a wide range of operating conditions. In this paper we present a novel configurable architecture for implementation of K-best algorithm. The proposed architecture is fully parallel and can support QPSK, 16-QAM and 64-QAM modulation schemes for a range of K values.

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

A 4 GHz ADPLL-based integer-N frequency synthesizer is reported in this paper. It employs a low-complexity digital phase and frequency detector as well as a non-linear phase and frequency decision circuit to significantly reduce the hardware complexity while maintain a comparable in-lock performance to other high-complexity ADPLLs. The ADPLL was fabricated in 90 nm CMOS technology to prove its feasibility. Operating with a high-frequency-resolution DCO, the proposed low-complexity ADPLL exhibits a programmable loop bandwidth from 100 kHz to 6 MHz with and an excellent in-band phase noise performance.

A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution

This paper reports a LC-based digitally controlled oscillator (DCO) with an enhanced frequency resolution and an extended linear frequency tuning range. It has a center frequency of 3.3 GHz. and a frequency tuning range of 600 MHz covered by 64 different frequency bands. Each frequency band has 2048 linear tuning levels with a frequency step of 5 kHz. This DCO was implemented in 90 nm CMOS and the measured frequency tuning characteristics arc provided in this paper. The DCO exhibits a phase noise of -11 NdBc/Hz. at 1 MHz frequency offset. The DCO core consumes 2 mA current from 1.2 V supply.

Event-Driven Modeling and Simulation of an Digital PLL

An event-driven modeling and simulation technique, implemented in Matlab is presented in this paper. It enables rapid and accurate simulation as it only calculates the time instants of interest. This technique is successfully applied to behavioral modeling and simulation of a digital phase-locked loop. The simulation environment retains the flexibility of modeling and mathematical manipulation that characterizes Matlab. For example, it allows time-domain modeling phase noise of each component of a digital PLL