Qingqing Chen

The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions

This paper introduces a new architecture for circuit-based Physical Unclonable Functions (PUFs) which we call the Bistable Ring PUF (BR-PUF). Based on experimental results obtained from FPGA-based implementations of the BR-PUF, the quality of this new design is discussed in different aspects, including uniqueness and reliability. On the basis of the observed complexity in the challenge-response behavior of BR-PUFs, we argue that this new PUF could be a promising candidate for Strong PUFs. Our design shows noticeable temperature sensitivity, but we discuss how this problem can be addressed by additional hardware and protocol measures.

Towards electrical, integrated implementations of SIMPL systems

This paper discusses strategies for the electrical, integrated implementation of a novel security tool termed SIMPL system, which was introduced in [1]. SIMPL systems are a public key version of Physical Unclonable Functions (PUFs). Like a PUF, each SIMPL system S is physically unique and non-reproducible, and implements an individual function FS. In opposition to a PUF, every SIMPL system S possesses a publicly known numerical description D(S), which allows its digital simulation and prediction. However, any such simulation must work at a detectably lower speed than the real-time behavior of S. As argued in [1], SIMPL systems have practicality and security advantages over PUFs, Certificates of Authenticity (COAs), Physically Obfuscated Keys (POKs), and also over standard mathematical cryptotechniques. This manuscript focuses on electrical, integrated realizations of SIMPL systems, and proposes two potential candidates: SIMPL systems derived from special SRAM-architectures (so-called “skew designs” of SRAM cells), and implementations based on analog computing arrays called Cellular Non-Linear Networks (CNNs).

Characterization of the bistable ring PUF

The bistable ring physical(ly) unclonable function (BR-PUF) is a novel electrical intrinsic PUF design for physical cryptography. FPGA prototyping has provided a proof-of-concept, showing that the BR-PUF could be a promising candidate for strong PUFs. However, due to the limitations (device resources, placement and routing) of FPGA prototyping, the effectiveness of a practical ASIC implementation of the BR-PUF could not be validated. This paper characterizes the BR-PUF further through transistor-level simulations. Based on process variation, mismatch, and noise models provided or suggested by industry, these simulations are able to provide predictions on the figures-of-merit of ASIC implementations of the BR-PUF. This paper also suggests a more secure way of using the BR-PUF based on its supply voltage sensitivity.

Application of mismatched Cellular Nonlinear Networks for Physical Cryptography

This paper proposes the use of Cellular Non-Linear Networks (CNNs) as physical uncloneable functions (PUFs). We argue that analog circuits offer higher security than existing digital PUFs and that the CNN paradigm allows us to build large, unclonable, and scalable analog PUFs, which still show a stable and repeatable input-output behavior. CNNs are dynamical arrays of locally-interconnected cells, with a cell dynamics that depends upon the interconnection strengths to their neighbors. They can be designed to evolve in time according to partial differential equations. If this If this equation describes a physical phenomenon, then the CNN can simulate a complex physical system on-chip. This can be exploited to create electrical PUFs with high relevant structural information content. To illustrate our paradigm at work, we design a circuit that directly emulates nonlinear wave propagation phenomena in a random media. It effectively translates the complexity of optical PUFs into electrical circuits.

Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping

Abstract Hardware monitoring information can be used during system runtime to increase system lifetime and reliability. Examples of such monitoring information are power, temperature, and the aging status of processors. They provide the system with relevant information about the current hardware health. Such information is especially crucial in resource-aware computing concepts that introduce self-organizing behavior to deal with large MPSoCs (Multi-Processor Systems-on-Chip): For resource-aware computing, resources are allocated according to the current requirements. To find suitable resource-application pairs and achieve system targets like optimizing the utilization, current hardware status must be considered during resource allocation. To evaluate and optimize resource allocation strategies during the design phase, FPGA prototyping is often required before its implementation in ASIC. The evolution of power, temperature and aging differ between ASIC implementation and FPGA prototype. The FPGA prototype should react on sensor data characterized from the target ASIC design instead of FPGA’s hardware status. This paper describes the design of an emulated ASIC Temperature and Power Monitoring system (eTPMon) for FPGA-based prototyping. The emulation approach for power monitors is based on an instruction-level energy model. For emulating temperature monitors, a thermal RC model is used. eTPMon can supply MPSoC prototypes with the hardware status information (power and temperature of the cores) needed for efficient load distribution, achieving resource-aware computing targets. Based on the eTPMon data, different operating strategies and control targets were evaluated for a 2-tile resource-aware MPSoC system. Values provided by eTPMon are usable for extracting information about the aging of processors, which can be used for increasing the system lifetime.

Dark silicon management: an integrated and coordinated cross-layer approach

Abstract This paper presents an integrated and coordinated cross-layer sensing and optimization flow for distributed dark silicon management for tiled heterogeneous manycores under a critical temperature constraint. We target some of the key challenges in dark silicon for manycores, such as: directly focusing on power density/temperature instead of considering simple per-chip power constraints, considering tiled heterogeneous architectures with different types of cores and accelerators, handling the large volumes of raw sensor information, and maintaining scalability. Our solution is separated into three abstraction layers: a sensing layer (involving hardware monitors and pre-processing), a dark silicon layer (that derives thermally-safe mappings and voltage/frequency settings), and an agent layer (used for selecting the parallelism of applications and thread-to-core mapping based on alternatives/constraints from the dark silicon layer).

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays

Massively Parallel Processor Arrays (MPPAs) can be nicely used in portable devices such as tablets and smartphones. However, applications running on mobile platforms require a certain performance level or quality (e.g., high-resolution image processing) that need to be satisfied while adhering to a certain power budget and temperature threshold. As a solution to the aforementioned challenges, we consider a resource-aware computing paradigm to exploit runtime adaptation without violating any thermal and/or power constraint in a programmable MPPA. For estimating the power consumption, we developed a mathematical model based on the post-synthesis implementation of an MPPA in different CMOS technologies while the temperature variation was emulated. We showcase our hardware/software mechanism to load new, on-the-fly configurations into the accelerator, considering quality/throughput tradeoffs for image processing applications. The results show that the average power consumption of a Sobel and Laplace operators using different number of processing elements amounts to 1.24 mW and 10.35 mW, respectively. Furthermore, only 1.64 μs are necessary for configuring a class of MPPA running at 550 MHz.

Emulation of an ASIC power and temperature monitor system for FPGA prototyping

Monitoring information can be used during system runtime to increase system lifetime and reliability. Examples of such monitoring information are power or temperature values. They provide the system with relevant information about the current hardware health. In a resource-aware computing system, where resources are allocated according to current requirements, the current hardware status must be included in the decisions for resource allocation in order to select the best suitable application-resource pairs and at the same time reach system targets like limiting the system temperature.To test and optimize the systems resource allocation already in the design phase, FPGA prototyping is often required before its implementation in an ASIC. Since the behavior of measured power and temperature evolution in FPGA and ASIC differ, data from power and temperature sensors on both platforms would have significant differences. To efficiently test and optimize the resource allocation for an ASIC implementation, it is necessary to provide the FPGA prototype with modeled power and temperature values characterized from an ASIC implementation. This paper describes how to emulate the behavior of an emulated ASIC power and temperature monitor system (eTPMon) on FPGA. The approach for emulating the power monitor is based on an instruction-level energy model. For emulating the temperature monitor, a thermal RC model is used. It is shown that eTPMon can supply an invasive MPSoC with the hardware status information (power and temperature of the cores) needed for efficient resource-aware load distribution to develop a resource-aware computing system concept. As a proof of concept different operating strategies and control targets were evaluated for a 2-tile invasive MPSoC.

MWA Skew SRAM Based SIMPL Systems for Public-Key Physical Cryptography

SIMulation Possible, but Laborious (SIMPL) systems are a novel cryptographic concept for physical cryptography that have been suggested in recent years. They can potentially solve inherent vulnerabilities of conventional public-key cryptography that is based on unproven mathematical hypotheses. The security of SIMPL systems rests on their physical unclonability and on the runtime difference between the real-time behavior of the unique SIMPL system and any adversarial simulation or emulation of it. One first circuit-based realization of SIMPL systems via so-called skew SRAMs has previously been discussed in the literature. This paper presents an approach to enhance the security of skew SRAM based SIMPL systems by introducing more complicated and parallel computing behavior taking place in the skew SRAM, which we call multiple-wordline-activation (MWA) skew SRAM. Simulations of the MWA skew SRAM show expected behavior complexity that can be taken advantage of in SIMPL systems to amplify the speed advantage over emulators (functional physical clones) or simulators (digital clones), which plays a key role in the security of SIMPL systems.