Qinke Wang

Power-aware placement

Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register clustering that reduces clock power by placing registers in the same leaf cluster of the clock trees in a smaller area and (2) activity-based net weighting that reduces net switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. The method applies to designs with multiple clocks and gated clocks. We implemented the method and obtained experimental results on 8 real-world designs after placement, routing, extraction and analysis. The power-aware placement method achieved on average 25.3% and 11.4% reduction in net switching power and total power respectively with 2.0% timing, 1.2% cell area and 11.5% runtime impact. This method has been incorporated into a commercial physical design tool.

A faster implementation of APlace

APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and density approximation functions. We speed up the placer using a hybrid usage of wirelength and density approximaions during he course of multi-level placement, and obtain 2-2.5 imes speedup of global placement on the IBM ISPD04 and ISPD05 benchmarks. Recent applications of the APlace framework to supply voltage degradation-aware placement and lens aberration-aware timing-driven placement are also briefly described.

The Y-Architecture for On-Chip Interconnect: Analysis and Methodology

The Y-architecture for on-chip interconnect is based on pervasiveuse of 0-, 120-, and 240-degree oriented semi-global and globalwiring. Its use of three uniform directions exploits on-chip routingresources more efficiently than traditional Manhattan wiring architecture.This paper gives in-depth analysis of deployment issues associatedwith the Y-architecture. Our contributions are as follows:(1) We analyze communication capability (throughput of meshes)for different interconnect architectures using a multi-commodityflow approach and a Rentian communication model. Throughput ofthe Y-architecture is largely improved compared to the Manhattanarchitecture, and is close to the throughput of the X-architecture.(2) We propose a symmetrical Y clock tree structure with bettertotal wire length compared to both H and X clock tree structures,and better path length compared to the H tree. (3) We discuss powerdistribution under the Y-architecture, and give analytical and SPICEsimulation results showing that the power network in Y-architecturecan achieve 8.5% less IR drop than an equally-resourced power networkin Manhattan architecture. (4) We propose the use of via tunnelsand banks of via tunnels as a technique for improving routabilityfor Manhattan and Y-architectures.

APlace: a general analytic placement framework

We streamline and extend APlace, the general analytic placement engine based on ideas of Naylor et al. [7] and described in [3, 4, 5]. Previous work explored the adaptability of APlace to multiple contexts with good quality of results. For example, the framework was extended to traditional wirelength-driven standard-cell placement in [3, 5], achieving good results in placed HPWL and routed final wire-length. The framework was also extended to top-down multilevel placement, congestion-directed placement, mixed-size placement, timing-driven placement, I/O-core co-placement and constraint handling for mixed-signal contexts [3, 4, 5]. In this work, we have modified the implementation of APlace for speed and scalability. Improvements have been made in clustering, legalization and detailed placement strategies, as well as via a distributable solution framework for both global and detailed placement phases.

Optimal planning for mesh-based power distribution

Robust power distribution within available routing area resources is critical to chip performance and reliability. In this paper, we propose a novel and efficient method for optimizing worst-case static IR-drop in hierarchical, uniform power distribution networks. Our results can be used for planning of hierarchical power distribution in early design stages, so that for a fixed total routing area the worst-case IR-drop on the power mesh is minimal, or for a given IR-drop tolerance the power mesh achieves the IR-drop specification with minimal routing area. Our contributions are as follows. (1) We derive a closed-form approximation for the worst-case IR-drop on a single-level power mesh. The formula shows that for a given total routing area, the worst-case IR-drop increases logarithmically with the number of metal lines on the mesh. (2) Based on the previous analysis and empirical studies, we propose a model for the worst-case static IR-drop on a two-level power mesh, and obtain an accurate empirical expression. (3) Using this expression, we present a novel approach to optimize the two-level mesh topology. (4) We extend our study to three-level power meshes, and find that a third, middle-level mesh helps to reduce IR-drop by only a relatively small extent (about 5%, according to our experiments).

Multi-project reticle floorplanning and wafer dicing

Multi-project Wafers (MPW) are an efficient way to share the rising costs of mask tooling between multiple prototype and low production volume designs. Packing the different die images on a multi-project reticle leads to new and highly challenging floorplanning formulations, characterized by unusual constraints and complex objective functions. In this paper we study multi-project reticle floorplanning and wafer dicing problems under the prevalent side-to-side wafer dicing technology. Our contributions include practical mathematical programming algorithms and efficient heuristics based on interval-graph coloring which find side-to-side wafer dicing plans with maximum yield for a fixed multi-project reticle floorplan and given per-die maximum dicing margins. We also give novel shelf packing and simulated annealing reticle floorplanning algorithms for maximizing wafer-dicing yield. Experimental results show that our algorithms improve wafer-dicing yield significantly compared to existing industry tools and academic min-area floorplanners.

Supply voltage degradation aware analytical placement

Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus on design and optimization of power/ground supply networks. In this paper, we propose supply voltage degradation aware placement, e.g., to reduce maximum supply voltage degradation by relocation of supply current sources. We represent supply voltage degradation at a P/G node as a function of supply currents and effective impedances (i.e., effective resistances in DC analysis) in a P/G network, and integrate supply voltage degradation in an analytical placement objective. For scalability and efficiency improvement, we apply random-walk, graph contraction and interpolation techniques to obtain effective resistances. Our experimental results show an average 20.9% improvement of worst-case voltage degradation and 11.7% improvement of average voltage degradation with only 4.3% wirelength increase.

Lens Aberration Aware Timing-Driven Placement

Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, variations induced by lens aberrations have been considered random due to their small extent. However, as process margins reduce, and as improvements in reticle enhancement techniques control variations due to other sources with increased efficacy, lens aberration-induced variations gain importance. For example, our experiments indicate that lens aberration can result in up to 8% variation in cell delay. In this paper, we propose an aberration-aware timing-driven analytical placement approach that accounts for aberration-induced variations during placement. Our approach minimizes the designs cycle time and prevents hold-time violations under systematic aberration-induced variations. On average, the proposed placement technique reduces cycle time by ~ 5% at the cost of ~ 2% increase in wire length

Lens aberration aware placement for timing yield

Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, variations induced by lens aberrations have been considered random due to their small extent. However, as process margins reduce, and as improvements in reticle enhancement techniques control variations due to other sources with increased efficacy, lens aberration-induced variations gain importance. For example, our experiments indicate that delays of most cells in the Artisan TSMC 90nm library are affected by 2--8% due to lens aberration. Aberration-induced variations are systematic and depend on the location in the lens field. In this article, we first propose an aberration-aware timing analysis flow that accounts for aberration-induced cell delay variations. We then propose an aberration-aware timing-driven analytical placement approach that utilizes the predictable slow and fast regions created on the chip due to aberration to improve cycle time. We study the dependence of our improvement on chip size, as well as use of the technique along with field blading which allows partial reticle exposure. We evaluate our technique on two testcases, AES and JPEG implemented in 90nm technology. The proposed technique reduces cycle time by 4.322% (80ps) at the cost of 1.587% increase in trial-routed wirelength for AES. On JPEG, we observe a cycle time reduction of 5.182% (132ps) at the cost of 1.095% increase in trial-routed wirelength.

Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement

Increasingly significant power/ground (P/G) supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction, which requires stochastic analysis and optimization techniques. We represent the supply voltage degradation at a P/G node as a function of the supply currents and the effective resistance of a P/G supply network and propose an efficient stochastic system-level P/G supply voltage prediction method, which computes P/G supply network effective resistances in a random walk process. We further propose to reduce P/G supply voltage degradation via placement of supply current sources, and integrate P/G supply voltage degradation reduction with conventional placement objectives in an analytical placement framework. Our experimental results show that the proposed stochastic P/G supply network prediction method achieves 10x-100x speedup compared with traditional SPICE simulation, and the proposed P/G supply voltage degradation aware placement achieves an average of 20.9% (11.7%) reduction on maximum (average) supply voltage degradation with only 4.3% wirelength increase.