Puneet Sharma

Eyecharts: constructive benchmarking of gate sizing heuristics

Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algorithms. We develop a method to generate benchmark circuits (called eyecharts) of arbitrary size along with a method to compute their optimal solutions using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose the weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 54% (Vt-assignment), 46% (gate sizing) and 49% (gate-length biasing) for realistic libraries and circuit topologies.

Accurate Predictive Interconnect Modeling for System-Level Design

We propose new accurate predictive models for the delay, power, and area of buffered interconnects to enable a more effective system-level design exploration with existing and future nanometer technology processes. We show that our models are significantly more accurate than previous models - essentially matching sign-off analyses. We integrate our models in the COSI-OCC communication synthesis infrastructure and show how they impact the feasibility and optimality of the network-on-chip architectures that are synthesized by this tool.

Lens aberration aware placement for timing yield

Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, variations induced by lens aberrations have been considered random due to their small extent. However, as process margins reduce, and as improvements in reticle enhancement techniques control variations due to other sources with increased efficacy, lens aberration-induced variations gain importance. For example, our experiments indicate that delays of most cells in the Artisan TSMC 90nm library are affected by 2--8% due to lens aberration. Aberration-induced variations are systematic and depend on the location in the lens field. In this article, we first propose an aberration-aware timing analysis flow that accounts for aberration-induced cell delay variations. We then propose an aberration-aware timing-driven analytical placement approach that utilizes the predictable slow and fast regions created on the chip due to aberration to improve cycle time. We study the dependence of our improvement on chip size, as well as use of the technique along with field blading which allows partial reticle exposure. We evaluate our technique on two testcases, AES and JPEG implemented in 90nm technology. The proposed technique reduces cycle time by 4.322% (80ps) at the cost of 1.587% increase in trial-routed wirelength for AES. On JPEG, we observe a cycle time reduction of 5.182% (132ps) at the cost of 1.095% increase in trial-routed wirelength.

Convergent Automated Chip Level Lithography Checking and Fixing at 45nm

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.

Calibration of library element optimization to improve static power

Library elements (or standard cells) are basic building blocks of integrated circuits. These are built early in the technology cycle. Small changes to library elements can result in significant power/performance changes to large designs instantiating them. Qualifying these small changes on silicon can benefit products. Several physical layout optimizations are performed to improve performance and/or reduce standby power. This paper demonstrates the application of ring oscillators to calibrate such optimizations. These ring oscillators are designed to provide cell-specific validation and feedback to the entire library optimization. Silicon calibration results from 55nm technology node are discussed.

Test circuits to characterize setup/hold/access times, minimum voltage and maximum frequency of operation for memory compilers

This paper will explain the design methodology to accurately measure the setup/hold/access time/Vmin & Fmax of memories on silicon. This architecture scheme implements the high resolution fine-tune delays of a few pico-seconds along with the coarse step sizes of tens to hundreds of pico-seconds depending on technology, along with BIST for memory Vmin & Fmax characterization. This architecture has been implemented on one of our test-chip and silicon measurements show that measured parameters results are within 10% range of the simulated values. Implemented design scheme also ensures the serial as well as parallel measurement of these parameters of the memory instances in order to save the expensive tester time.

Efficient technique for Si validation of level shifters

This paper presents a new structure that uses an addressable parametric array to validate level shifter cells. This structure is very area efficient and allows direct measurement of input and output voltages. Being a parametric structure enabled direct measurement of the output voltages, a critical parameter for level shifters. Experimental data confirmed the utility of this approach, validating level shifters in three different power domains including source biasing on the same 22-pad design. The simulation results show good correlation with the measured data.

In-design hierarchical DFM closure for DFM-clean IP

This paper presents the requirements for the Design for Manufacturability (DFM) checks such as lithography, and Chemical and Mechanical Polishing (CMP) at 28nm technology node, and the need to perform these DFM checks, early in the design phase and with minimum overhead. As a result, this reduces the risk of uncovering some DFM issues at the design tape out time when the changes in a design become expensive. Because IP blocks can be targeted to multiple designs, it is a key requirement that the lithography and CMP checks are accurate and designer-friendly and are easily applied at block-level. This paper describes the block-based methodology that allows the IP designers to perform quickly a comprehensive DFM analysis, including lithography and long-range CMP effects. This paper also explains the integration of the DFM checks into the design flow and correlation results between the block and chip-level checks.

Analysis of layout-dependent context effects on timing and leakage in 28nm

In advanced process technologies, a layout context (that is the layout surrounding a cell) can impact the timing and leakage of a cell due to stress induced by the layout features, Well Proximity Effect (WPE), and other layout-dependent effects. The Litho Electrical Analyzer (LEA) tool from Cadence® is used to perform an analysis on 28nm standard cells in order to assess the variation in the timing and leakage characteristics due to the layout-dependent effects. During the study, the substantial leakage and timing shifts due to the layout contexts were observed. Moreover, the leakage variations were measured, and different levels of correlation of shifts across the PMOS transistors and the corresponding non-correlation between the PMOS and NMOS devices were also observed. Due to cancellation of the positive and negative variations in leakage, and because the leakage variation in Silicon is large, it is recommended to include a flat leakage margin without having added complexity to the leakage analysis flow. In addition, the timing was observed that impacts the slew and load conditions and identified conditions where shifts would be the greatest. Also, several mitigations were identified to reduce the variability of timing due to a context. This paper begins with describing the tools and methodologies used for the performance and power analysis of standard cells. It also explains the delay impact analysis, present delay simulation, Silicon-based results, and proposes guidelines to mitigate the un-modeled LDEs.

Practical implementation of via and wire optimization at the SoC level

In recent years, various DFM techniques are developed and adopted by the designers to improve circuit yield and reliability. The benefits from applying a DFM technique to a circuit often come at the expense of degrading other process or design attributes. In this paper, we discuss two widely deployed techniques: double vias and wire spreading/widening, show the benefits and trade-offs of their usage, and practical ways to implement them in SoC designs.