Qinwen Fan

A 1.8

This paper presents a low-power precision instrumentation amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 μV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The instrumentation amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm2 chip area (0.2 mm2 with the DC servo loop) and consumes 1.8 μA current (2.1 μA with the DC servo loop) from a 1 V supply.

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This paper describes the design of a precision instrumentation amplifier. It employs chopping to reduce its offset and 1/f noise, and the resulting ripple caused by the up-modulated offset and 1/f noise is suppressed by a ripple reduction loop. A multi-path architecture is used to eliminate the transfer function notch that would otherwise be introduced by the ripple reduction loop. The amplifier is implemented in a standard 0.7 μm CMOS technology and draws 143 μA current from a 5 V supply. Its input-referred noise is 21 nV/√Hz and its residual offset is less than 2× μV (12 samples). The instrumentation amplifier can also be configured as a general-purpose opamp with half the noise and offset, but which dissipates the same amount of power.

W 60 nV

This paper presents a theoretical analysis and measurements of the current noise of several chopper instrumentation amplifiers, which demonstrate that the charge injection and clock feed-through associated with the MOSFETs of the input chopper give rise to significant input current and current noise. In combination with high source impedances, this “chopper noise” is converted to voltage noise, which may then be a significant contributor to the amplifiers total input-referred voltage noise. Chopper noise has a white power spectral density, whose magnitude is roughly proportional to the chopping frequency. Design guidelines are proposed to reduce chopper noise, as well as the use of a clock-bootstrapped chopper, which generates significantly less noise than a traditional chopper.

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Capacitively coupled chopper amplifiers are capable of handling common-mode voltages outside their supply rails, while also achieving high power efficiency and low offset [1-3]. However, a significant drawback of such amplifiers is a transfer-function notch around the chopping frequency (fchop). This is because their input choppers demodulate signals near fchop to DC, where they are blocked by the input capacitors. This problem is exacerbated by the use of a ripple-reduction loop (RRL) to suppress chopper ripple, which also creates a notch at fchop, and, moreover, can take up to 1ms to settle. The net result is an amplifier with a transfer-function notch and a step response that is accompanied by a slowly-decaying burst of chopper ripple [1]. To solve these problems, a multi-path capacitively-coupled chopper-stabilized operational amplifier (MCCOPA) is proposed. Implemented in a HV CMOS 0.7μm technology, it has a smooth transfer function and achieves a 20V common-mode voltage range (CMVR), 3μV offset and 148dB DC CMRR while drawing only 8μA from a 5V supply.

Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes

This paper presents simulations and measurements of the input impedance, input bias and offset current of a chopped multi-path current feedback instrumentation amplifier. In precision applications, these parameters, together with a finite impedance source can lead to significant measurement errors. In this paper, design strategies to minimize these errors are provided. At a chopping frequency of 30 kHz, the proposed amplifier has an input impedance of 6 MΩ, with bias and offset currents of 102pA and 43pA, respectively. In addition, it achieves low noise (21nV/√Hz), low (2 µV) input-referred offset, high common-mode rejection ratio (134dB) and high power supply rejection ratio (120dB).

A 21 nV/

This paper describes a capacitively coupled chopper instrumentation amplifier (CCIA) for current-sensing applications. A capacitively driven input chopper enables a ±30V input common-mode (CM) range and an input offset less than 5μV. The CCIA does not draw supply current from its input terminals or require a separate high-voltage (HV) supply; and has a common-mode rejection ratio (CMRR) in excess of 160dB, both of which represent significant improvements on the state-of-the-art [1-3]. Implemented in a HV CMOS 0.7μm technology, the CCIA achieves an NEF of 6.1 (6.5× better than [1-3]), while drawing only 26μA from a 3V supply.

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This paper describes a precision capacitively-coupled chopper instrumentation amplifier (CCIA). It achieves 1µV offset, 134dB CMRR, 120dB PSRR, 0.16% gain accuracy and a noise efficiency factor (NEF) of 3.1, which is more than 3x better than state-of-the-art. It has a rail-to-rail DC common-mode (CM) input range. Furthermore, a positive feedback loop (PFL) is used to boost the input impedance, and a ripple reduction loop (RRL) is used to reduce the ripple associated with chopping. The CCIA occupies only 0.1mm2 in a 65nm CMOS technology. It can operate from a 1V supply, from which it draws only 1.8µA.

Hz Chopper-Stabilized Multi-Path Current-Feedback Instrumentation Amplifier With 2

This paper explains how the charge injection and clock feed-through of MOSFET switches causes significant input currents and current noise in chopper amplifiers. The current noise can be modeled as a form of shot noise with a white power spectral density (PSD). Both the input current and its noise PSD increase linearly with the chopping frequency. This has been verified by measurements on identical chopper amplifiers with different types of input choppers. Some design guidelines are proposed, as well as a low-noise input chopper based on a reduced-swing (Vdd/2) bootstrapped clock driver.

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Amplifiers with low offset and low 1/f noise usually employ auto-zeroing (AZ) and/or chopping. However, AZ suffers from noise aliasing, and so requires more power dissipation for a given noise specification. Chopping, although free of noise aliasing, requires notch filters [1, 2] or AZ [3] to remove the ripple caused by up-modulated offset and 1/f noise. This paper describes a chopper-stabilized multi-path current-feedback instrumentation amplifier (CFIA), whose ripple is removed by a continuous-time (CT) ripple-reduction loop (RRL) [2]. In contrast to [2], the notch created by the RRL is eliminated by the use of a multi-path architecture. This results in a CFIA with a smooth single-pole response, which also achieves low offset (2µV) and low noise (21nV/√Hz) in a power efficient manner (NEF=9.6). By appropriately connecting its inputs, the CFIA can also be used as an opamp. In this configuration, its offset is further reduced while its noise and NEF are halved.

V Offset

This paper presents a capacitively-coupled chopper operational amplifier whose maximum input common-mode voltage far exceeds its 5V supply. To achieve low offset, it employs a capacitively-driven input chopper, which can handle the wide input common-mode voltage with low power dissipation. To suppress chopping ripple, it employs an area-efficient switched-capacitor ripple-reduction loop. Implemented in a high-voltage 0.7μm CMOS technology, the amplifier achieves 3μV offset and an NEF of 5.1, while consuming 10μA. The chip has an active area of 1.2mm2.