Refet Firat Yazicioglu

A 60

There is a growing demand for low-power, small-size and ambulatory biopotential acquisition systems. A crucial and important block of this acquisition system is the analog readout front-end. We have implemented a low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals. Key to its performance is the new AC-coupled chopped instrumentation amplifier (ACCIA), which uses a low power current feedback instrumentation amplifier (IA). Thus, while chopping filters the 1/f noise of CMOS transistors and increases the CMRR, AC coupling is capable of rejecting differential electrode offset (DEO) up to plusmn50 mV from conventional Ag/AgCl electrodes. The ACCIA achieves 120 dB CMRR and 57 nV/radicHz input-referred voltage noise density, while consuming 11.1 muA from a 3 V supply. The chopping spike filter (CSF) stage filters the chopping spikes generated by the input chopper of ACCIA and the digitally controllable variable gain stage is used to set the gain and the bandwidth of the front-end. The front-end is implemented in a 0.5 mum CMOS process. Total current consumption is 20 muA from 3V

\mu

This paper gives an overview of the results of BMECs Human++ research program. This program aims to achieve highly miniaturized and autonomous sensor systems that enable people to carry their personal body area network. The body area network will provide medical, lifestyle, assisted living, sports or entertainment functions. It combines expertise in wireless ultra-low power communications, packaging, 3D integration technologies, MEMS energy scavenging techniques and low-power design techniques.

W 60 nV/

This paper presents the design and implementation of an analog signal processor (ASP) ASIC for portable ECG monitoring systems. The ASP ASIC performs four major functionalities: 1) ECG signal extraction with high resolution, 2) ECG signal feature extraction, 3) adaptive sampling ADC for the compression of ECG signals, 4) continuous-time electrode-tissue impedance monitoring for signal integrity monitoring. These functionalities enable the development of wireless ECG monitoring systems that have significantly lower power consumption yet that are more capable than their predecessors. The ASP has been implemented in 0.5 μm CMOS process and consumes 30 μW from a 2 V supply. The noise density of the ECG readout channel is 85 nV/√Hz and the CMRR is better that 105 dB. The adaptive sampling ADC is capable of compressing the ECG data by a factor of 7 and the heterodyne chopper readout extracts the features of the ECG signals. Combination of these two features leads to a factor 4 reduction in the power consumption of a wireless ECG monitoring system. Furthermore, the proposed continuous-time impedance monitoring circuit enables the monitoring of the signal integrity.

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Several studies have demonstrated that understanding certain brain functions can only be achieved by simultaneously monitoring the electrical activity of many individual neurons in multiple brain areas [1]. Therefore, the main tradeoff in neural probe design is between minimizing the probe dimensions and achieving high spatial resolution using large arrays of small recording sites. Current state-of-the-art solutions are limited in the amount of simultaneous readout channels [2], contain a small number of electrodes [2,3] or use hybrid implementations to increase the number of readout channels [3,4].

Hz Readout Front-End for Portable Biopotential Acquisition Systems

This paper presents an active electrode system for gel-free biopotential EEG signal acquisition. The system consists of front-end chopper amplifiers and a back-end common-mode feedback (CMFB) circuit. The front-end AC-coupled chopper amplifier employs input impedance boosting and digitally-assisted offset trimming. The former increases the input impedance of the active electrode to 2 GΩ at 1 Hz and the latter limits the chopping induced output ripple and residual offset to 2 mV and 20 mV, respectively. Thanks to chopper stabilization, the active electrode achieves 0.8 μVrms (0.5-100 Hz) input referred noise. The use of a back-end CMFB circuit further improves the CMRR of the active electrode readout to 82 dB at 50 Hz. Both front-end and back-end circuits are implemented in a 0.18 μm CMOS process and the total current consumption of an 8-channel readout system is 88 μA from 1.8 V supply. EEG measurements using the proposed active electrode system demonstrate its benefits compared to passive electrode systems, namely reduced sensitivity to cable motion artifacts and mains interference.

Human++: autonomous wireless sensors for body area networks

An ECG signal processing method with quad level vector (QLV) is proposed for the ECG holter system. The ECG processing consists of the compression flow and the classification flow, and the QLV is proposed for both flows to achieve better performance with low-computation complexity. The compression algorithm is performed by using ECG skeleton and the Huffman coding. Unit block size optimization, adaptive threshold adjustment, and 4-bit-wise Huffman coding methods are applied to reduce the processing cost while maintaining the signal quality. The heartbeat segmentation and the R-peak detection methods are employed for the classification algorithm. The performance is evaluated by using the Massachusetts Institute of Technology-Bostons Beth Israel Hospital Arrhythmia Database, and the noise robust test is also performed for the reliability of the algorithm. Its average compression ratio is 16.9:1 with 0.641% percentage root mean square difference value and the encoding rate is 6.4 kbps. The accuracy performance of the R-peak detection is 100% without noise and 95.63% at the worst case with -10-dB SNR noise. The overall processing cost is reduced by 45.3% with the proposed compression techniques.

A 30

A biopotential readout front-end can be configured to extract EEG, ECG, and EMG signals and draws 20muA from 3V. AC coupling of chopped amplifiers results in an input-referred noise of 60nV/radicHz and CMRR of 120dB at 1kHz. The immunity of the CMRR to electrode offset voltages is improved with an active input stage and 110dB CMRR is achieved at 100Hz with 50mV electrode offset

\mu

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μW from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring

This paper proposes a 3-channel biopotential monitoring ASIC with simultaneous electrode-tissue impedance measurements which allows real-time estimation of motion artifacts on each channel using an an external μC. The ASIC features a high performance instrumentation amplifier with fully integrated sub-Hz HPF rejecting rail-to-rail electrode-offset voltages. Each readout channel further has a programmable gain amplifier and programmable 4th order low-pass filter. Time-multiplexed 12 b SAR-ADCs are used to convert all the analog data to digital. The ASIC achieves >; 115 dB of CMRR (at 50/60 Hz), a high input impedance of >; 1 GΩ and low noise (1.3 μVrms in 100 Hz). Unlike traditional methods, the ASIC is capable of actual motion artifact suppression in the analog domain before final amplification. The complete ASIC core operates from 1.2 V with 2 V digital IOs and consumes 200 μW when all 3 channels are active.

An implantable 455-active-electrode 52-channel CMOS neural probe

With the advent of ultra-low power sensor interfaces, long-term ambulatory monitoring using wearable devices and more energy-autonomous implants are becoming a reality. This paper will present suitable architectures and circuits, and will present several application case examples.