Qiuping Huang

Warpage and Reliability of a 3D-MCM on an Embedded Substrate With Multiple Interconnection Method

In this paper, the warpage of 3-D multichip module (3D-MCM) on an embedded substrate with flip-chip and wirebonding interconnection method was studied by finite element (FE) simulation and moire fringes measurement. Simulation results showed that the warpage of 3D-MCM without underfill presents double-bow-shaped (W-shaped) mode, which is because of the cavity in substrate and the viscoplasticity behavior of solder balls. For the same reason, the warpage of substrate with temperature change has an inflexion around 75 °C, which indicated that the cavity in the substrate center may decrease the warpage of the substrate. The FE model and simulation results were validated through moire fringes measurement. Based on this model, the effect of underfill on warpage was discussed. It turned out that using suitable underfill could strengthen the interconnection between component and substrate, and then protect the solder balls and decrease the warpage of module. However, underfill with high coefficient of thermal expansion (CTE) may increase the stress, strain and plastic work density of solder ball, therefore result in the solder ball failure and lower the reliability of the module. The optimal CTE of the underfill, which is the mean magnitude of CTEs of the materials at both sides of unferfill layer, was determined with multiobjective method.

Development of indium bumping technology through AZ9260 resist electroplating

Indium bumping is very critical technology in the application of high-density interconnection between a FPA (focal plane array) and a Si ROIC (read-out integrated circuit) by flip-chip bonding. In this paper, the indium BGA (ball grid array) chips are prepared with an electroplating method on the Si substrate. With such a method, the first difficulty arises in removing the seed layer. Two ways, including IBE (ion beam etching) and lift-off, are adopted to overcome it. The results show that the lift-off process is effective but not IBE. During the reflow process, many indium bumps fall off the substrate. Two ways are tried to solve this problem: one is to optimize the reflow profile and the other is to thicken the wetting layer. The results show that these two ways can effectively improve such status. The barrier effects of the UBM (under bump metallization) for indium, which are Ti/Pt (300 ?/200 ?) and Ti/Pt/Au/Ep Au (300 ?/200 ?/1000 ?/4 ?m), are also investigated. Experimental results indicate that both of them can be used in application of integration of the FPA and ROIC. Reliability of indium bumps with these two kinds of UBM is evaluated by the shear test. The results show that their shear strength has a significant increase after reflow. For the indium bump with UBM of Ti/Pt/Au/Ep Au (300 ?/200 ?/1000 ?/4 ?m), IMC (intermetallic compounds) at the interface of Au?In can strengthen the indium bump but may change the plasticity of indium.

Indium bump fabricated with electroplating method

Indium solderbumps are usually used in interconnection between focal plane arrays (FPAs) and Si read out integrated circuits (ROICs) by flip-chip bonding. The fabrication of indium bump array is a critical technology in this process. In this paper, the 16×16 indium bump array was fabricated by electroplating method. The indium bump is 100μm in pitch and 40μm in diameter. Lift-off method and IBE process were adopted to try to remove the seed layer. Ti/Pt/Au(200 Å/300 Å/800Å) by sputtering method and Ti/Pt/Au/ep Au(200 Å/300 Å/800Å/3–4μm) by electroplating after sputtering were investigated as UBM (under bump metallization) of indium bump. The reliability of indium bumps with different UBM was evaluated by cross-section analysis and shear test.

Development of three-dimensional multichip module based on embedded substrate with multiple interconnections

A new type of 3D multichip module (3D-MCM) for wireless sensor network was developed based on a kind of embedded FR-4 substrate for the wireless sensor network, in which FCOB (flip-chip on board), COB (chip on board), BGA (ball grid array) technologies, wirebonding and flip-chip interconnection technologies were combined together. The PBGA device and bare die were hybrid-integrated on the embedded multi-layer FR-4 substrate. By solder ball placement and reflow the BGA was formed at the bottom of 3D-MCM, and solder balls with different melting points were used for initial and final vertical interconnections for the sake of compatibility of all levels interconnections of BGA by reflow soldering. The application of embedded substrate solved the problem that the top surface of the encapsulated chip overtops the solder balls in the condition that the chip was assembled in the same side of substrate with BGA. The thermal management was conducted and the thermal related reliability of 3D-MCM were simulated and evaluated respectively. This kind of packaging structure satisfies the electrical performance and thermal requirement, and meets the challenge of minimization, high reliability and low cost of the package design for the wireless network.

A novel MEMS package with three-dimensional stacked modules

A 3D stacked modular packaging technology was developed so as to meet the general requirements of MEMS and wireless communication on packaging. The general requirements include high-density, low-cost and high-yield etc. According to the requirements of modular package, a kind of accelerator (MEMS) and its modem circuits (IC) were incorporated by three stacked modules and a 3D stacked modular package was realized. In this package, every module was assembled by using traditional surfaced mounting technology (SMT) based on FR4 substrate. MEMS and IC devices were assembled in the same module. The vertical interconnection between modules was realized by means of solder paste printer, mechanical alignment apparatus and optimized reflow curve. The mechanical alignment apparatus was specially prepared for alignment and positioning of stacked modular assembly. The alignment of stacked modules was completed by the alignment-pin/hole method. In order to increase the alignment efficiency, the module substrate was design as paste-up, for example 3×3. The alignment precision of vertical interconnection of the stacked modules reaches to 0.068mm typically. The volume of the entire stacked module was about 19mm×19mm×8mm. Finally, the influencing factors on the vertical interconnection were discussed and shear strength test of the module was presented.

Analysis of the phenomenon of falling off of indium bumps from substrate during reflow process

Indium bumping is a crucial technology in FPAs (focal plane array) application. In this paper, electroplating method is tried to prepare the indium bump arrays. But one difficulty appears during the reflow process. In such process, many indium bumps fall off from the substrate. To solve such problem, its possible causes are discussed and the corresponding measures are taken. Experimental results show that the measures can effectively improve status of the falling off of indium bumps, which is consistent with the reasonable analysis. To analyze the influence of reflow process to the stress in the bump system, finite element analysis with ANSYS is adopted in this paper.

Development of flip-chip interconnections of photodetector readout circuit (ROIC)

In this paper, the interconnection between 16×16 photodetector ROIC and substrate for the ROIC test was developed. Three kinds of substrate methods, i.e. high-density organic substrate, silicon interposer substrate and through-silicon-via (TSV) technology, were adopted. Three corresponding technical process flows were designed, and corresponding experiments were conducted. Finally, the interconnection between photodetector ROIC and substrates as well as the test of ROIC performance were realized. Above three solutions were compared and evaluated in process realizability, interconnection performance and cost etc. It turns out that TSV method is considered as the advanced and ideal interconnection solution for the test of 16×16, 32×32 and 64×64 photodetector ROIC.