Wenguo Ning

FEA study of the evolution of wafer warpage during reflow process in WLP

In this paper, the evolution of wafer warpage during reflow process in wafer level packaging (WLP) is investigated by finite element analysis (FEA). The investigation focuses on three different fan-in WLP technologies: ball on polymer WLP without under bump metallurgy (UBM), ball on polymer WLP with thick UBM layer and encapsulated copper post WLP. Both wafer-level model and ball-level model are built and the results indicate that wafer warpage derived from ball-level model is compatible with wafer-level model. Ball on polymer WLP with thick UBM layer has the maximum warpage after reflow process. Reflow profiles with different cooling rate are also simulated.

Experimental identification of warpage origination during the wafer level packaging process

Redistribution layer (RDL) composing of polyimide (PI) dielectric layer and electro-chemical deposited (ECD) Cu trace is a critical part for wafer level packaging (WLP). One concern of this multi-layered film structure is the wafer warpage induced during the process, which poses threats to automatic handling, 3-D integration and device reliability. In this paper, the warpage origination during the WLP process was identified and analyzed by experiments and simulations. The wafer warpage evolution during the WLP process was measured by a Multi-beam Optical Sensor system. We found that the cure shrinkage of PI has little effect on the warpage, however, it is mainly caused by the coefficient of thermal expansion (CTE) mismatch between the deposited materials. The ECD Cu trace in RDL accounted for a substantial proportion to the total wafer warpage and lead to a hysteresis response during the thermal processes indicating plastic deformation has taken place. For in-depth understanding, the plastic behavior of ECD Cu film was investigated and the kinematic hardening plastic model was established. Finally, the stresses distribution in RDL structure was simulated by numerical method and the influence of ECD Cu trace pattern on the wafer warpage was evaluated.

Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature (Tg) of polyimide will help to reduce the final wafer warpage.

An MCM package process for 24GHz driver amplifier using photosensitive BCB

This paper presents a wafer-level microwave multichip module (MMCM) packaging process for 24GHz driver amplifier using photosensitive-Benzocyclobutene (photo-BCB) of 25µm. It is developed for multilayer interconnection of monolithic microwave integrated chip (MMIC). A 24GHz driver amplifier chip is embedded in a wet-etched trench on 4 inch lossy Si wafer and covered with a layer of BCB as dielectrics. Microstrip lines are fabricated with two layers of metal patterns to connect pads on MMIC with the test pads on MCM package in case of excessive loss. The interlayer connection resistance of this metal/BCB interconnection structure is tested with interconnection chain structures through Kelvin resistance measurement. The electrical characteristics of the package are also illustrated. The gain of the amplifier (S21) after packaging is more than 22dB from 21GHz to 26 GHz, and the S21 changes when packaged is less than 2 dB. The return loss S11 and S22 is less than −14.1dB and −17.3dB from 21GHz to 26GHz.

Analysis of thermal stresses in redistribution layer of WLP with different arrangement of interconnections

Thick polyimide film and electroplated Cu lines are widely adopted in redistribution layer of wafer level packaging. One potential reliability problem is the stresses generated in the thermal process. In this paper, the evolution of thermal stresses and plastic strain in two-level interconnections in redistribution layer of WLP was analyzed by recourse to the finite element analysis and Taguchi method. Cu lines embedded in polyimide with different aspect ratio, aligned vertically or arranged in a staggered manner were considered. Attention was devoted to the thermal stresses and plastic strain evolution and their dependency on the geometry structure. The constitutive response of Cu was taken to be elastic-plastic, with the post-yield behavior following the kinematic hardening model. The stresses and plastic strain are found to be a little higher in the low-level lines, for both aligned and staggered arrangements. A larger aspect ratio is helpful to reduce the stress, but it will generate large plastic deformation. The aspect ratio also plays a key role in wafer curvature and large aspect ratio will decrease the curvature.

Application of WLP with barrier trench structure in precision screen printing technology by glass frit

This paper reports on glass frit wafer bonding, which is a universally usable technology for Micro-Electronics Mechanical System (MEMS) wafer level encapsulation and packaging. The package process demonstrated from DEK-APi screen printing of glass frit, firing to wafer bonding by glass frit. However, the dimensions of glass frit after bonding are nonuniform and some frit widens to reach MEMS device, resulting in package failure. A new improved technology (Barrier trench technology, BTT) is developed. And in process of bonding, glass frit expanding in bonding force is resisted by the BTT. The uniformity of bonded glass frit dimension can be achieved. It allows hermetic sealing and a high process yield. And shear test, water test for the gross leak and fine leak test results fulfilled the corresponding MIL-STD.

A novel MEMS package with three-dimensional stacked modules

A 3D stacked modular packaging technology was developed so as to meet the general requirements of MEMS and wireless communication on packaging. The general requirements include high-density, low-cost and high-yield etc. According to the requirements of modular package, a kind of accelerator (MEMS) and its modem circuits (IC) were incorporated by three stacked modules and a 3D stacked modular package was realized. In this package, every module was assembled by using traditional surfaced mounting technology (SMT) based on FR4 substrate. MEMS and IC devices were assembled in the same module. The vertical interconnection between modules was realized by means of solder paste printer, mechanical alignment apparatus and optimized reflow curve. The mechanical alignment apparatus was specially prepared for alignment and positioning of stacked modular assembly. The alignment of stacked modules was completed by the alignment-pin/hole method. In order to increase the alignment efficiency, the module substrate was design as paste-up, for example 3×3. The alignment precision of vertical interconnection of the stacked modules reaches to 0.068mm typically. The volume of the entire stacked module was about 19mm×19mm×8mm. Finally, the influencing factors on the vertical interconnection were discussed and shear strength test of the module was presented.

A novel redistribution layer tailored by nanotwinned copper decreases warpage in wafer level packaging

As a common problem in wafer lever packaging(WLP), wafer warpage caused by heat process should be carefully controlled in case of product inaccuracy or yield loss, and redistribution layer (RDL), as a key structure of WLP, is one of the major concerns that causes warpage. In this paper, a novel RDL tailored by pulsed electrodeposited nanotwinned copper (nt-Cu) was introduced into WLP. It was found that grains grew larger and nt-Cu became rare in our novel RDL when it underwent 300°C annealing. Compared with traditional RDL consisting of normal electroplated copper, the novel RDL revealed quite different warpage characteristics when heating to 300°C for the first time, which was probably due to thermal stability and high yield stress of nt-Cu. Namely, twin lamina growth rather than grain growth during annealing helps nt-Cu avoid the sharp decrease of yield stress. Its very promising to take the advantage of nt-Cu to reduce wafer warpage.

Fabrication and microstructure evolution of preferred oriented nanotwinned copper by pulse electroplating for RDL in WLP

Nanotwinned copper is drawing widely attention for it simultaneously demonstrates high strength, high ductility, and high conductivity. It will be very beneficial to microelectronics in many respects, one of which is redistribution layer in wafer level packaging. We take advantage of (111) preferred oriented nanotwinned copper to fabricate 2-poly-1-metal (2P1M) redistribution layer in wafer level packaging. Nanotwinned copper was deposited by pulsed electroplating. Texture of copper can be controlled by seedlayer, thickness of films, or patterns, and texture can be observed by X-ray diffraction. Microstructure and the evolution of copper after annealing were studied by focused ion beam, scanning electron microscopy, and transmission electron microscopy.