R.B. Hulfachor

Scaling trends for device performance and reliability in channel-engineered n-MOSFETs

Channel-engineered MOSFETs with retrograde doping profiles are expected to provide increased carrier mobility and immunity to short channel effects. However, the physical mechanisms responsible for device performance of retrograde designs in the deep-submicron regime are not fully understood, and general device scaling trends are not well documented. Also, little effort has been devoted to the study of hot-electron-induced device degradation. In this paper, we employ a comprehensive simulation methodology to investigate scaling and device performance trends in channel-engineered n-MOSFETs. The method features an advanced ensemble Monte Carlo device simulator to extract hot-carrier reliability for super-steep-retrograde and more conventional silicon n-MOS designs with effective channel lengths scaled from 800 to 100 nm. With decreasing channel length, our simulations indicate that the retrograde design shows increasingly less total hot-electron injection into the oxide than the conventional design. However, near the 100-nm regime, the retrograde design provides less current drive, loses its advantage of higher carrier mobility, and exhibits much greater sensitivity to hot-electron-induced interface states when compared to the conventional device.

An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications

Performance and reliability of deep-submicron MOSFETs employing super-steep-retrograde (SSR) channel doping configurations are examined using self-consistent Monte Carlo and drift-diffusion simulations. It is found that SSR channel doped MOSFETs provide increased current drive and reduced threshold voltage shift when compared with conventional MOSFET structures. However, they also display a relatively higher substrate current and interface state generation rate. The physical mechanisms of performance enhancement/degradation and design tradeoffs for SSR channel doped MOSFETs are discussed. >

Comparative analysis of hot electron injection and induced device degradation in scaled 0.1 μm SOI n-MOSFETs using Monte Carlo simulation

A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 /spl mu/m SOI n-MOSFETs operating under low voltage conditions, i.e., V/sub d/ considerably less than the Si-SiO/sub 2/ injection barrier height /spl phi//sub b/. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding /spl phi//sub b/. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 /spl mu/m SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T/sub Si/ experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface.

Spatial retardation of carrier heating in scaled 0.1-/spl mu/m n-MOSFET's using Monte Carlo simulations

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 /spl mu/m n-MOSFETs under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V/sub d/ considerably less than the Si/SiO/sub 2/ injection barrier height /spl phi//sub b/. Simulation of both devices reveal that 1) although qV/sub d/</spl phi//sub b/, carriers can obtain energies greater than /spl phi//sub b/, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 /spl mu/m n-MOSFET designs exhibit comparable drain current degradation rates.

Effects of silicon layer properties on device reliability for 0.1-/spl mu/m SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-/spl mu/m SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10/sup 16/ cm/sup -3/) channel and 2) a heavily-doped (10/sup 18/ cm/sup -3/) channel. For each design, the silicon layer thicknesses (T/sub Si/) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO/sub 2/ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T/sub Si/ results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead.

Channel engineering in n-MOSFETs: scaling trends for hot electron injection and device degradation

Drain engineering has been the primary focus of efforts to overcome reliability trade-offs dictated by channel hot electron injection (CHEI) into the oxide in MOSFET devices. Comparatively few studies on channel, or vertical, engineering have been conducted, though recently there has been increased interest in its applications. In this study we employ a reliability simulation package to investigate the potential of channel engineering for future silicon technology by comparing scaling trends of CHEI and device sensitivity to the resulting distributions of induced interface damage for both Super-Steep-Retrograde (SSR) channel designs and more conventional (CONV) channel designs.

Monte Carlo Simulation for Reliability Physics Modeling and Prediction of Scaled (100 nm) Silicon Mosfet Devices

Since the early 1970’s, silicon integrated circuit technology has been propelled by continual and successful efforts to reduce the active channel length of MOSFET devices [1–3]. This exercise in scaling provides the framework that has produced increases in the density of devices on a chip, increases in device frequency response and operating speed, and increases in the precision required to achieve more complex systems with greater functionality and performance. Today, devices with channel lengths well below 100 nm have been produced in many research laboratories, and the downward scaling trends of the past twenty years are expected to persist at the same pace until at least the 40 nm generation in manufacturing [1], or about the year 2015. This level of technology is expected to correspond to 128 GBit DRAMs and 28 Ggate microprocessors with five times the clock frequency and 1/9 the power consumption of today’s devices, all operating at a power supply voltage of around 0.5 V.

A Monte Carlo study of drain and channel engineering effects on hot electron injection and induced device degradation in 0.1 /spl mu/m n-MOSFETs

To investigate hot carrier phenomena in 0.1 /spl mu/m n-MOSFETs under low-voltage conditions, we employ a comprehensive Monte Carlo simulator to compare hot electron injection into the oxide for a variety of drain and channel design strategies. Pertinent features of the Monte Carlo simulator include: (1) electron-electron scattering, which is significant in producing the high energy tail in the electron energy distribution; (2) an enhanced particle statistics algorithm to provide detail in the high energy tail; and (3) a coupled two-dimensional numerical solution to Poissons equation that is rapidly recalculated every 0.1 fs to provide a self-consistent, dynamic electric field distribution. In addition, we examine relative device reliability in the variety of 0.1 /spl mu/m designs by first combining hot electron injection distributions provided by Monte Carlo simulations with an empirical model to generate interface state distributions and next incorporating these interface states into SPISCES to calculate induced changes in device characteristics.