R. B. M. Cross

Investigating the stability of zinc oxide thin film transistors.

The stability of thin film transistors incorporating sputtered ZnO as the channel layer is investigated under gate bias stress. Positive stress results in a positive shift of the transfer characteristics, while negative stress results in a negative shift. Low bias stress has no effect on the subthreshold characteristics. This instability is believed to be a consequence of charge trapping at/near the channel/insulator interface. Higher biases and longer stress times cause degradation of the subthreshold slope, which is thought to arise as a consequence of defect state creation within the ZnO channel material. After all stress measurements, the devices recover their original characteristics at room temperature without any annealing.

A low temperature combination method for the production of ZnO nanowires

The growth of large-area, patterned and oriented ZnO nanowires on silicon using a low temperature silicon-CMOS compatible process is demonstrated. Nanowire synthesis takes place using a thin nucleation layer of ZnO deposited by radiofrequency magnetron sputtering, followed by a hydrothermal growth step. No metal catalysts are used in the growth process. The ZnO nanowires have a wurtzite structure, grow along the c-axis direction and are distributed on the silicon substrate according to the pre-patterned nucleation layer. Room temperature PL measurements of the as-grown nanowires exhibit strong yellow-red emission under 325 nm excitation that is replaced by ultraviolet emission after annealing. This method can be used to integrate patterned 1D nanostructures in optoelectronic and sensing applications on standard silicon CMOS wafers.

A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

The performance and stability of thin-film transistors with zinc oxide as the channel layer are investigated using gate bias stress. It is found that the effective channel mobility, ON/OFF ratio, and subthreshold slope of the devices that incorporate SiN are superior to those with SiO2 as the dielectric. The application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. The devices also demonstrate a logarithmic time-dependent threshold voltage shift suggestive of charge trapping within the band gap and the band tails responsible for the deterioration of device parameters. It is postulated that this device instability is partly a consequence of the lattice mismatch at the channel/insulator interface. All stressed devices recover to near-original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

The Effect of Gate-Bias Stress and Temperature on the Performance of ZnO Thin-Film Transistors

The stability of ZnO thin-film transistors is investigated by using gate-bias stress. It is found that the application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. It is postulated that this device instability is a consequence of charge trapping at or near the channel/insulator interface. In addition, there is a degradation of subthreshold behavior and channel mobility, which is suggested to result from the defect-state creation within the ZnO layer. The effect of elevated temperature stress shows a predominance of interface-state creation in comparison to trapping under gate-bias stress. Device instability appears to be a consequence of the charging and discharging of preexisting trap states at the interface and in the channel region of the devices. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

Creativity - a catalyst for technological innovation

Technological innovation is one of the most important aspects of a companys competitiveness. The dynamics of market and technological changes require a company to focus on creativity and innovation to support technological developments and sustain competitive advantage. A new model is introduced in this paper to illustrate the relationship between creativity and technological innovation.

Investigating the Stability of Thin Film Transistors with Zinc Oxide as the Channel Layer

The stability of thin film transistors with zinc oxide as the channel layer is investigated using gate bias stressing techniques. It is found that the application of low positive and negative stress results in the device transfer characteristics shifting in positive and negative directions respectively. However, low bias has no effect on the subthreshold characteristics. It is postulated that this device instability is a consequence of charge trapping at or near to the channel/insulator interface. The application of higher biases and longer stress times cause a degradation of subthreshold behaviour and is suggested to result from defect state creation within the ZnO layer. Similar behaviour is exhibited at elevated measurement temperatures. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

Electrically Air-stable ZnO Thin Film Produced by Reactive RF Magnetron Sputtering for Thin Film Transistors Applications

The influence of native point defects on the electrical and optical stability of zinc oxide (ZnO) layers in air produced by reactive RF magnetron sputtering is investigated. ZnO thin films are strongly affected by oxygen (O 2 ) molecules in ambient atmosphere. For instance, surface defects such as oxygen vacancies act as adsorption sites of O2 molecules, and the chemisorption of O 2 molecules depletes the surface electronic states and reduces channel conductivity. Thin films of ZnO produced have electrical resistivities between 8.6 × 10 3 and 8.3 × 10 8 Ω-cm, and were found to be electrically-stable in air. TFTs fabricated using these films exhibited effective mobilities of ∼3 cm 2 V -1 s -1 and the threshold voltage shifts by 4 s.

High voltage polycrystalline thin-film transistor with variable doping slots in the offset region

Performance of a high voltage polycrystalline Si thin-film transistor (TFT) with variable doping slots in the offset region is demonstrated in this letter. In the proposed structure, the width of the doping slots and the gaps increase from the drain toward the gate edge. Compared to offset-drain (OD) TFT fabricated on the same substrate, the proposed structure exhibits an increase in on current by a factor of 15 at 0.1 V drain bias and by an order at 10 V drain bias. The device also shows a more saturate drain characteristic. The blocking capability is 152 V, which is almost the same as the OD TFT and is attributed to the voltage sharing across the doping slots.

The Impact of Fermi Pinning on Thermal Properties of the Instabilities in ZnO TFTs

In this paper we describe gate bias and temperature induced device instabilities of inverted-staggered ZnO-TFTs. It is shown that low positive and negative gate bias results in the transfer characteristics shifting in a positive and negative direction respectively. It is suggested that this is a consequence of temporary charge trapping at or close to the channel/insulator interface. The degradation of device parameters such as the threshold voltage, subthreshold slope and effective channel mobility is demonstrated at elevated measurement temperatures, suggesting the generation of defects and/or trap states in the interfacial region. In addition, it is postulated from the extracted activation energy of the drain current that the Fermi-level is pinned during the operation of the devices due to the high level of states close to the conduction band edge. These results highlight the relatively ease with which defects could be created at the interface, indicating a high concentration of weak or strained bonds. Both charge trapping and defect creation-induced instabilities appear to be reversible, as all devices regain their original characteristics after a period of relaxation at room temperature.

A novel method for the growth of low temperature silicon structures for 3-D flash memory devices

Low temperature (≤400°C) growth of polycrystalline silicon (poly-Si) is carried out using plasma-enhanced chemical vapour deposition. After an initial preparation step poly-Si was grown on the substrates. Optical band gap studies of the poly-Si films have been correlated to hydrogen content of the films as well as to their photoconductivity. Furthermore, the suitability of these films for use as information storage materials for future generation 3-D flash memory devices is investigated using capacitance-voltage ( C-V ) measurements via metal-insulator-semiconductor device structures. C-V analysis indicates strong charge storage behavior for the poly-Si films.