E.M. Sankara Narayanan

A low temperature combination method for the production of ZnO nanowires

The growth of large-area, patterned and oriented ZnO nanowires on silicon using a low temperature silicon-CMOS compatible process is demonstrated. Nanowire synthesis takes place using a thin nucleation layer of ZnO deposited by radiofrequency magnetron sputtering, followed by a hydrothermal growth step. No metal catalysts are used in the growth process. The ZnO nanowires have a wurtzite structure, grow along the c-axis direction and are distributed on the silicon substrate according to the pre-patterned nucleation layer. Room temperature PL measurements of the as-grown nanowires exhibit strong yellow-red emission under 325 nm excitation that is replaced by ultraviolet emission after annealing. This method can be used to integrate patterned 1D nanostructures in optoelectronic and sensing applications on standard silicon CMOS wafers.

XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit

Record performance of a novel power transistor integrated in a 0.35 μm power IC technology is reported. Measured specific on-state resistance of 33 mOhm*mm2 for a 94 V breakdown is breaking the silicon-limit and is the lowest reported value to date. The device outperforms its nearest rival by a factor of 2.5. The device consists of the stacking of a vertical MOS on a fully depleted vertical drift layer, leading to a high cell density

A novel double RESURF LDMOS for HVIC's

Abstract The viability of a fully implanted double RESURF technology using a linearly varying doping of p-layer at the surface [Electron. Lett. 32 (12) (1996) 1092–1093] is demonstrated for the first time. Incorporating such a layer allows the drift region charge to be doubled without degradation of breakdown voltage. Experimental results of a high-voltage LDMOS in such a technology show a reduction in the on-resistance by one-half of that of a conventional RESURF based structure.

Polycrystalline silicon thin film transistor incorporating a semi-insulating field plate for high voltage circuitry on glass

The fabrication and enhanced performance of a polycrystalline silicon high voltage thin film transistor structure, which incorporates a semi-insulating field plate, are reported. For comparison, the performance of conventional offset drain and metal field plate structures, fabricated on the same wafer using the same low temperature (⩽610 °C) polycrystalline silicon process, is described. Electrical characterization of the high voltage thin film transistor structures demonstrates that the new three terminal device offers the highest blocking capability (>200 V) without sacrificing on state performance.

Experimental Demonstration of a 1.2kV Trench Clustered Insulated Gate Bipolar Transistor in Non Punch Through Technology

For the first time, we present experimental results of a trench clustered IGBT structures fabricated in 1.2kV non-punch-through technology. Experimental results demonstrate significantly low forward voltage drop in comparison to trench IGBTs in the same technology. Furthermore, results show that the use of dummy cells in the TCIGBT device can improve the trade-off between the on-state and turn-off losses

A segmented anode, npn controlled lateral insulated gate bipolar transistor

Abstract A fast switching area efficient segmented npn anode lateral insulated gate bipolar transistor is proposed. Segments of p + and npn are incorporated at the anode along the width in the third dimension instead of placing them linearly along the drift length of the device. The p-base parameters of the npn segment and the ratio of the p + and npn segments are found to strongly influence the switching behaviour.

Progress in silicon RF Power MOS technologies - current and future trends

In this paper, the current progress and factors limiting the performance of silicon RF Power device technologies are reviewed. Silicon VDMOSFETs have high linearity but the gain is low at frequencies in excess of 1 GHz. LDMOSFETs have higher gain and can operate up to 2.4 GHz. However, the linearity and reliability of LDMOSFETs is poor in comparison to VDMOSFETs. New architectures and evolving trends are discussed.

A novel area efficient floating field limiting ring edge termination technique

In this paper, a floating ring edge termination structure using minimally sized lightly doped p-rings is proposed. A novel embodiment of the structure involves placement of shallow p(+)-regions offset from the centre of each of the p-well rings to reduce peak electric field at the surface and to reduce sensitivity to oxide interface charges. The structures have been fabricated using an advanced, 2 kV MOS-bipolar process technology. A close match between the simulated and experimental results validates the proposed structure.

Progress in MOS-controlled bipolar devices and edge termination technologies

An overview of the recent developments in high-voltage power semiconductor MOS-controlled bipolar devices is presented. The Insulated Gate Bipolar Transistor (IGBT) technology is explored from its initial stage up to the latest state-of-the-art developments, in terms of cathode engineering, drift design and anode engineering to highlight the different approaches used for optimisation and the achieved trade-offs. Further, several MOS-gated thyristors, which are aimed to replace the IGBT, are analysed. Moreover, the present paper reviews the various approaches in the fabrication of edge termination used in power device MOS-controlled bipolar devices.

Performance of 200 V CMOS compatible auxiliary cathode lateral insulated gate transistors

The authors report the performance of various anode-shorted auxiliary cathode lateral insulated gate transistor (ACLIGT) structures fabricated using a 2.5 mu m digital CMOS compatible HVIC process. The reverse breakdown voltage of the ACLIGT is comparable to that of an equivalent anode shorted lateral insulated gate transistor (LIGT). The results indicate that, by placing an auxiliary cathode and an extended p-buried layer of an anode-shorted LIGT, the holes flowing into the p-well can be diverted to overcome the latch-up problems of the LIGT in an ACLIGT. The LIGT shows latch-up at 140 mA, which corresponds to a current density of 340 A/cm/sup 2/ while the ACLIGT structures do not show latch-up. The measured turn-off characteristics of the ACLIGT reveal a turn-off time of less than 250 ns while an equivalent LIGT shows a turn-off time of 350 ns.<<ETX>>