R. E. Makon

Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation

This paper compares three single-ended distributed amplifiers (DAs) realized in an in-house InP/InGaAs double heterojunction bipolar transistor technology featuring an f/sub t/ and f/sub max/ larger than 200 GHz. The amplifiers use five or eight gain cells with cascode configuration and emitter follower buffering. Although the technology is optimized for mixed-signal circuits for 80 Gbit/s and beyond, DA results could be achieved that demonstrate the suitability of this process for the realization of modulator drivers. The results are documented with scattering parameter, eye diagram, and power measurements. This includes amplifiers featuring a 3-dB bandwidth exceeding 80 GHz and a gain of over 10 dB. One of the amplifiers exhibits clear eyes at 80 Gbit/s with a gain of 14.5 dB and a voltage output swing of 2.4 V/sub pp/ limited by the available digital input signal. This amplifier delivers an output power of 18 dBm (5.1 V/sub pp/) at 40 GHz and 1-dB compression. Two amplifiers offer a tunable gain peaking, which can be used to optimize circuit performance and to compensate losses in the circuit environment. The results show that, using our InP/InGaAs technology, an integration of high-speed mixed-signal circuits (e.g., multiplexers) and high-power modulator drivers on a single chip is feasible.

InP-based DHBT technology for high-speed mixed signal and digital applications

We report on an InP DHBT-based technology featuring current gains of ∼ 90, breakdown voltages of ≫ 4.5 V and cut-off frequency (fT) values of ≫ 300 GHz. Using this technology, state-of-the-art mixed signal integrated circuits, including distributed amplifiers (DAs), multiplexers (MUX) / demultiplexers (DEMUX), and clock and data recovery (CDR) ICs suitable for 100+ Gbit/s applications have been demonstrated. The DA-MMICs achieved gains of ∼ 21 dB, 3-dB bandwidths of ≥ 95 GHz (gain-bandwidth-products ≫ 1 THz), as well as output voltages of up to 3 V at 100 Gbit/s. A monolithically integrated CDR/1:2 DEMUX IC has also successfully been tested at data rates of up to 107 Gbit/s.

112 Gb/s field trial of complete ETDM system based on monolithically integrated transmitter & receiver modules for use in 100GbE

112 Gb/s field trial demonstration of a complete ETDM system based on monolithically integrated transmitter and receiver modules was achieved for the first time, with BER performance below FEC error-free threshold at 231 −1 PRBS tributary data word-length.

InP DHBT Based IC Technology for over 80 Gbit/s Data Communications

In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signal and monolithic microwave integrated circuits. The InGaAs/InP DHBTs were grown by MBE and fabricated using conventional process techniques. Devices with an emitter junction area of 4.8μm 2 exhibited peak cutoff frequency (f T ) and maximum oscillation frequency (f MAX ) values of 265 and 305 GHz, respectively, and a breakdown voltage (BV CEo ) of over 5 V. Using this technology, a set of mixed-signal IC building blocks for > 80Gbit/s fibre optical links, including distributed amplifiers (DA), voltage controlled oscillators (VCO), and multiplexers (MUX), have been successfully fabricated and operated at 80 Gbit/s and beyond.

100 Gbit/s Fully Integrated InP DHBT-Based CDR/1:2 DEMUX IC

In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is presented. The integrated circuit (IC) is realized using an in-house InP double heterostructure bipolar transistor (DHBT) technology exhibiting cut-off frequency values of more than 300 GHz for both fT and fmax. The CDR IC consists mainly of a half-rate linear phase detector including a 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). A 100 Gbit/s data signal at the corresponding input of the CDR circuit gives rise to 50 Gbit/s recovered and demultiplexed output data featuring clear eye opening and a voltage swing of 500 mVpp. The extracted 50 GHz clock signal from the input data features a voltage swing of 250 mVpp, while the corresponding peak-to-peak (pp) and rms jitter amount to 2.1 ps and 0.5 ps, respectively. The full IC dissipates 2.1 W at a single supply voltage of -4.5 V.

ETDM Transmitter Module for 100-Gb/s Ethernet

Performance of a packaged distributed-feedback travelling-wave electroabsorption modulator module for data transmission at 100 Gb/s is presented for the first time. Clearly open eye diagrams at 80 Gb/s with an extinction ratio (ER) of 4.9 dB and 100 Gb/s with ER 4.2 dB (limited by measurement setup) are demonstrated together with data transmission over 100-m-long standard single-mode fiber and over dispersion-compensated 10-km fiber link.

100 Gb/s ETDM Transmitter Module

Components of a 100 Gb/s transmitter with electrical time-division multiplexing are presented as following: electrical multiplexer, driver amplifier, and large-bandwidth distributed feedback-traveling-wave electro-absorption modulator module. The performance of the parts of the transmitter, as well as the complete chain, is investigated for data operation and transmission in future 100 Gb/s Ethernet (100GbE). Clearly open eye diagrams at 100 Gb/s are demonstrated together with data transmission over 300 m long standard single mode fiber link.

Fundamental low phase noise InP-based DHBT VCOs with high output power operating up to 75 GHz

Fundamental low phase noise MMIC VCOs with high output power using InP/InGaAs double heterostructure bipolar transistors (DHBTs) are reported. A first VCO with output buffer has been designed for +70 GHz operation and exhibits oscillation frequencies ranging from 70.9 GHz to 75 GHz. At 74 GHz, the VCO features a minimum phase noise of -97 dBc/Hz at 1 MHz offset frequency. Within the tuning range, a single ended output power up to 8 dBm was measured, resulting in a total signal power of 11 dBm. The second VCO version without output buffer was targeted for the 44 GHz range. The achieved operation frequencies range from 43.4 GHz to 48 GHz, with up to 2 dBm single-ended output power. At 48 GHz, a minimum phase noise of -102 dBc/Hz at 1 MHz offset frequency is achieved.

InP DHBT-Based IC Technology for 100-Gb/s Ethernet

It is now clear that 112-Gb/s data rate is the next step in the network evolution (100-Gb/s Ethernet). Due to its high speed and high breakdown voltage, the InP double-heterojunction bipolar transistor (DHBT) technology is particularly suited for signal processing and high-speed communication systems. This paper summarizes our InP DHBT device and integrated circuit (IC) technology developed for >; 100-Gb/s-class medium scale mixed-signal ICs. Key features and issues important for the growth and manufacturing of InP DHBTs with step-graded collectors are first discussed. The molecular-beam-epitaxy-grown transistors have cut-off frequencies (fT and fmax) of over 350 GHz, current gains of ~90, and common-emitter breakdown voltages of >; 4.5 V. Using this technology, we then fabricated and succeeded in 112-Gb/s testing of multiplexers and integrated clock and data recovery/1:2 demultiplexer ICs and modules with very clear eye waveforms. Using the same technology, a distributed amplifier intended for use as a modulator driver exhibited an output voltage swing of ~2 Vpp. These building-block ICs combine high-speed operation with high signal quality and enable 112-Gb/s optical fiber transmission.

InP DHBT-based ICs for 100 Gbit/s data transmission

This paper reports state-of-the-art mixed signal ICs, including a distributed amplifier and a multiplexer-core intended for use in 100 Gbit/s optical communication systems (Ethernet). Using a manufacturable InP DHBT technology, exhibiting current gains of >80 and cut-off frequencies (fT and fmax) of >300 GHz, the broadband amplifier achieved a gain of 21 dB and a 3-dB bandwidth of 95 GHz (GxBW>1 THz), whereas, the 2:1 multiplexer-core has been tested at data rates up to 138 Gbit/s.