R. Hatley

The Design and construction of the ZEUS central tracking detector

Abstract The mechanical, electrical and electronic design and construction of the ZEUS central tracking detector are described, together with the chamber monitoring and environmental control. This cylindrical drift chamber is designed for track reconstruction, electron identification and fast event triggering in a high beam-crossing rate, high magnetic field application.

Use of an FPGA to identify electromagnetic clusters and isolated hadrons in the ATLAS level-1 calorimeter trigger

Abstract At the full LHC design luminosity of 10 34 cm −2 s −1 , there will be approximately 10 9 proton–proton interactions per second. The ATLAS level-1 trigger is required to have an acceptance factor of ∼10 −3 . The calorimeter trigger covers the region | η |⩽5.0, and φ =0 to 2 π . The distribution of transverse energy over the trigger phase space is analysed to identify candidates for electrons/photons, isolated hadrons, QCD jets and non-interacting particles. The Cluster Processor of the level-1 calorimeter trigger is designed to identify transverse energy clusters associated with the first two of these. The algorithms based on the trigger tower energies which have been designed to identify such clusters, are described here. The algorithms are evaluated using an FPGA. The reasons for the choice of the actual FPGA being used are given. The performance of the FPGA has been fully simulated, and the expected latency has been shown to be within the limits of the time allocated to the cluster trigger. These results, together with the results of measurements made with real data into a fully configured FPGA, are presented and discussed.

Beam tests of a prototype level-1 calorimeter trigger for LHC experiments

Abstract Beam tests of a first-prototype electromagnetic calorimeter trigger processor for LHC experiments are described. The synchronous, pipelined, digital processor built with ASICs, was successfully operated at the full LHC bunch-crossing frequency of 40 MHz. Real data signals were obtained from a liquid argon electromagnetic calorimeter. The measured performance of the electron/photon trigger algorithm is compared with Monte Carlo simulations.

One Size Fits All : Multiple Uses of Common Modules in the ATLAS Level-1 Calorimeter Trigger

The architecture of the ATLAS Level-1 Calorimeter Trigger has been improved and simplified by using a common module to perform different functions that originally required three separate modules. The key is the use of FPGAs with multiple configurations, and the adoption by different subsystems of a common high-density custom crate backplane that takes care to make data paths equal widths and includes minimal VMEbus. One module design can now be configured to count electron/photon and tau/hadron clusters, or count jets, or form missing and total transverse-energy sums and compare them to thresholds. In addition, operations are carried out at both crate and system levels by the same module design.

Study of LVDS serial links for the ATLAS level-1 calorimeter trigger

This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 algorithmic processors from the Preprocessor crates. National Semiconductor’s Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit-error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10 13 per link can be achieved through compact cable connector assemblies over distances up to 20 m.

Prototype cluster processor module for the ATLAS level-1 calorimeter trigger

The Level-1 Calorimeter Trigger consists of a Preprocessor, a Cluster Processor (CP), and a Jet/Energy -sum Processor (JEP). The CP and JEP receive digitised triggertower data from the Preprocessor and produce trigger multiplicity and region-of-interest (RoI) information. The CP Modules (CPM) are designed to find isolated electron/photon and hadron/tau clusters in overlapping windows of trigger towers. Each pipelined CPM processes a total of 280 trigger towers of 8-bit length at a clock speed of 40 MHz. This huge I/O rate is achieved by serialising and multiplexing the input data. Large FPGA devices have been used to retrieve data and perform the cluster-finding algorithm. A full-specification prototype module has been built and tested, and first results will be presented.

The Final Multi-Chip Module of the ATLAS Level-1 Calorimeter Trigger Pre-processor

The final Pre-Precessor Multi-Chip Module (PPrMCM) of the ATLAS Level-1 Calorimeter Trigger is presented. It consists of a four-layer substrate with plasma-etched vias carrying nine dies from different manufacturers. The task of the system is to receive and digitize analog input signals from individual trigger towers, to perform complex digital signal processing in terms of time and amplitude and to produce two independent output data streams. A real-time stream feeds the subsequent trigger processors for recognizing trigger objects, and the other provides deadtime-free readout of the Pre-Processor information for the events accepted by the entire ATLAS trigger system. The PPrMCM development has recently been finalized after including substantial experience gained with a demonstrator MCM.

Implementation Of A First-level Calorimeter Trigger For Use At The Large Hadron Collider At CERN

A prototype first-level calorimeter trigger for use at LHC is described. The trigger is designed to operate on analogue signals sampled every 15 ns, the original design period for LHC. The prototype system takes in signals from a 6x6 array of calorimeter cells. These are digitised by FADCs and are then sent to a cluster finding module which contains nine ASICs based on a 0.8 micron CMOS gate array. Each ASIC searches for isolated energy clusters within the array and also calculates the sum of the energy in all 16 cells. The energy threshold of the cluster and of the isolation window are field programmable. The performance of the trigger has been evaluated both with test systems and in real conditions connected to a liquid-argon electromagnetic calorimeter in a test beam at CERN. The latency of this pipelined trigger system is 175 ns, including digitisation and digital processing.

Prototype Readout Module for the ATLAS Level-1 Calorimeter Trigger Processors

The level-1 calorimeter trigger consists of three subsystems, namely the Preprocessor, electron/photon and tau/hadron Cluster Processor (CP), and Jet/Energy-sum Processor (JEP). The CP and JEP will receive digitised calorimeter trigger-tower data from the Preprocessor and will provide trigger multiplicity information to the Central Trigger Processor and region-of-interest (RoI) information for the level-2 trigger. It will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. This paper will outline a readout system based on FPGA technology, providing a common solution for both DAQ readout and RoI readout for the CP and the JEP. Results of building a prototype readout driver (ROD) module will be presented, together with results of tests on its integration with level-2 and DAQ modules.

The electron/photon and tau/hadron Cluster Processor for the ATLAS First-Level Trigger - a Flexible Test System

The electron/photon and tau/hadron first-level trigger system for ATLAS will receive digitised data from approximately 6400 calorimeter trigger towers, covering a pseudo-rapidity region of ± 2.5. The system will provide electron/photon and tau/hadron trigger multiplicity information to the Central Trigger Processor, and Region of Interest information for the second-level trigger. The system will also provide intermediate results to the DAQ system for monitoring and diagnostic purposes. The system consists of four different 9U-module designs and two different chip (ASIC/FPGA) designs. This paper will outline a flexible test system for evaluating various elements of the system, including data links, ASICs/FPGAs and individual modules.