R. Iris Bahar

Algebraic decision diagrams and their applications

In this paper we present theory and experiments on the algebraic decision diagrams (ADDs). These diagrams extend BDDs by allowing values from an arbitrary finite domain to be associated with the terminal nodes. We present a treatment founded in Boolean algebras and discuss algorithms and results in applications like matrix multiplication and shortest path algorithms. Furthermore, we outline possible applications of ADDs to logic synthesis, formal verification, and testing of digital systems.

Power and energy reduction via pipeline balancing

Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%.

Power and performance tradeoffs using various caching strategies

In this paper, we propose several different data and instruction cache configurations and analyze their power as well as performance implications on the processor. Unlike most existing work in low power microprocessor design, we explore a high performance processor with the latest innovations for performance. Using a detailed, architectural-level simulator, we evaluate full system performance using several different power/performance sensitive cache configurations such as increasing cache size or associatively and including buffers along side L1 caches. We then use the information obtained from the simulator to calculate the energy consumption of the memory hierarchy of the system. As an alternative to simply increasing cache associatively or size to reduce lower-level memory energy consumption (which may have a detrimental effect on on-chip energy consumption), we show that, by using buffers, energy consumption of the memory subsystem may be reduced by as much as 13% for certain data cache configurations and by as much as 23% for certain instruction cache configurations without adversely effecting processor performance or on-chip energy consumption.

A Probabilistic-Based Design Methodology for Nanoscale Computation

As current silicon-based techniques fast approach their practicallimits, the investigation of nanoscale electronics, devices andsystem architectures becomes a central research priority. It is expectedthat nanoarchitectures will confront devices and interconnectionswith high inherent defect rates, which motivates the searchfor new architectural paradigms.In this paper, we propose a probabilistic-based design methodologyfor designing nanoscale computer architectures based onMarkov Random Fields (MRF). The MRF can express arbitrarylogic circuits and logic operation is achieved by maximizing theprobability of state configurations in the logic network. Maximizingstate probability is equivalent to minimizing a form of energythat depends on neighboring nodes in the network. Once we developa library of elementary logic components, we can link themtogether to build desired architectures based on the belief propagationalgorithm. Belief propagation is a way of organizing theglobal computation of marginal belief in terms of smaller localcomputations. We will illustrate the proposed design methodologywith some elementary logic examples.

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits

Many classes of applications, especially in the domains of signal and image processing, computer graphics, computer vision, and machine learning, are inherently tolerant to inaccuracies in their underlying computations. This tolerance can be exploited to design approximate circuits that perform within acceptable accuracies but have much lower power consumption and smaller area footprints (and often better run times) than their exact counterparts. In this paper, we propose a new class of automated synthesis methods for generating approximate circuits directly from behavioral-level descriptions. In contrast to previous methods that operate at the Boolean level or use custom modifications, our automated behavioral synthesis method enables a wider range of possible approximations and can operate on arbitrary designs. Our method first creates an abstract synthesis tree (AST) from the input behavioral description, and then applies variant operators to the AST using an iterative stochastic greedy approach to identify the optimal inexact designs in an efficient way. Our method is able to identify the optimal designs that represent the Pareto frontier trade-off between accuracy and power consumption. Our methodology is developed into a tool we call ABACUS, which we integrate with a standard ASIC experimental flow based on industrial tools. We validate our methods on three realistic Verilog-based benchmarks from three different domains - signal processing, computer vision and machine learning. Our tool automatically discovers optimal designs, providing area and power savings of up to 50% while maintaining good accuracy.

Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors

Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly by focusing efforts on mechanical or circuit design techniques. Now that we are reaching the limits of some of these past techniques, an architectural approach is fundamental to solving power related problems. In this work, we use a model of the Alpha 21264 to simulate a high-performance, multi-pipelined processor with two integer pipeline clusters and one floating point pipeline. We propose a hardware mechanism to dynamically monitor processor performance and reconfigure the machine on-the-fly such that available resources are more closely matched to the programs requirements. Namely, we propose to save energy in the processor by disabling one of the two integer pipelines and/or the floating point pipe at runtime for selective periods of time during the execution of a program. If these time periods are carefully selected, energy may be saved without negatively impacting overall processor performance. Our initial experiments shows on average total chip energy savings of 12% and as high as 32% for some benchmarks while performance degrades by an average of only 2.5% and at most 4.5%.

Parametric yield management for 3D ICs: Models and strategies for improvement

Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ICs by reducing the communication time between different chip components through the use of short TSV-based vertical wires. This reduction is particularly attractive in processors where it is desirable to reduce the access time between the main logic die and the L2 cache or the main memory die. Process variations in 2D ICs lead to a drop in parametric yield (as measured by speed, leakage and sales profits), which forces manufacturers to speed bin their chips and to sell slow chips at reduced prices. In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and profits of 3D ICs. Comparing our proposed strategies to current yield-oblivious methods, it is demonstrated that it is possible to increase the number of 3D ICs in the fastest speed bins by almost 2×, while simultaneously reducing the number of slow ICs by 29.4%. This leads to an improvement in performance by up to 6.45% and an increase of about 12.48% in total sales revenue using up-to-date market price models.

Computing the Maximum Power Cycles of a Sequential Circuit

This paper studies the problem of estimating worst case power dissipation in a sequential circuit. We approach this problem by finding the maximum average weight cycles in a weighted directed graph. In order to handle practical sized examples, we use symbolic methods, based on Algebraic Decision Diagrams (ADDs), for computing the maximum average length cycles as well as the number of gate transitions in the circuit, which is necessary to construct the weighted directed graph.

A probabilistic-based design for nanoscale computation

As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this chapter, we exam probabilistic-based design methodologies for designing nanoscale computer architectures based on Markov Random Fields (MRF) The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures. Overall, the probabilistic-based design can dynamically adapt to structural and signal-based faults.

A symbolic method to reduce power consumption of circuits containing false paths

Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing. Recently we have proposed a symbolic procedure which exploits the compactness of the ADD data structure to accurately calculate the arrival times at each node of a circuit for any primary input vector. In this paper we extend our timing analysis tool to the symbolic calculation of required times and slacks, and we use this information to identify gates of the circuits that can be re-sized. The nice feature of our approach is that it takes into account the presence of false paths naturally. As shown by the experimental results, circuits re-synthesized with the technique we present in this paper are guaranteed to be at least as fast as the original implementations, but smaller and substantially less power-consuming.