R.J. van de Plassche

Dynamic element matching for high-accuracy monolithic D/A converters

A novel way to obtain a very high accuracy in the bit weighting required for bipolar monolithic digital-to-analog (D/A) converters is described. The new method combines passive division using matched elements with a time division concept, needs no trimming, and is insensitive to element aging. A 12-bit monolithic D/A network with internal reference sources, built as a test circuit, demonstrates the versatility of this new technique.

An 8-b 650-MHz folding ADC

Where a flash analog-to-digital converter (ADC) needs 2/sup N/-1 comparators to convert an analog value into an N-bit binary code, an M-times folding ADC can perform this function needing slightly more than 2/sup N//M comparators. In the design reported, N=8 and the folding factor M=8. Reduction in the number of comparators is obtained by analog preprocessing of the ADC input signal. In the design considered, power consumption, chip area, and parasitic capacitance at the analog input of the ADC are reduced by using only four folding blocks and 8-times interpolation. >

An 8-bit 100-MHz full-Nyquist analog-to-digital converter

An 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The converter is implemented in an oxide-isolated bipolar process, requiring 800 mW from a single 5.2-V supply. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation. >

A high-speed 7 bit A/D converter

A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4/spl times/2.5 mm.

A 540-MHz 10-b polar-to-Cartesian converter

A 10-b polar-to-Cartesian converter for generating digital sine and cosine waveforms simultaneously with a maximum sample rate of 540 MHz is presented. The converter is derived from a coordinate rotation digital computer (CORDIC) processor. Implementation details and the chip layout are given. The converter is implemented in a 1- mu m 13-GHz triple-level interconnect bipolar process, requiring 1000 mW from a single 5-V supply. The die size is 25 mm/sup 2/. >

A wideband monolithic instrumentation amplifier

A voltage-to-current converter has been designed for an IC instrumentation amplifier. Paper will discuss features which include voltage gain, adjustable from 1-1000, cmrr of 106 dB and gain-independent bandwidth of 800 kHz.

A wide-band monolithic instrumentation amplifier [application of voltage-current convertor]

Describes a new voltage-to-current converter. This converter combines accuracy with differential signal handling and a high common-mode rejection ratio (CMRR). An application in an instrumentation amplifier consisting of two voltage-to-current converters in a balancing circuit shows the versatility of these units in analog circuit design. A remarkable point of the instrumentation amplifier is that the bandwidth (800 kHz) remains constant although the voltage gain varies from 1 to 10/SUP 4/.

A Monolithic 8-Bit Video A/D Converter

A monolithic 8-bit two-step flash type A/D converter has been designed. To obtain full resolution and good linearity at high frequencies, a double folding analog signal processing system is used. Delay time errors between the coarse and the fine quantizes used can be corrected for in this system. An on-chip input amplifier allows adjustment of the input sensitivity with a high input impedance and a low input capacitance. the 3 x 4.2 mm/sup 2/ chip made in a standard bipolar technology consumes 100 mA from a 5.2 V supply.

An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing

Successful implementation of folding and interpolation techniques in high-speed A/D converters has been demonstrated in both bipolar and, more recently, CMOS technology. The folding architecture can be considered as a time-continuous two-step architecture. This means that a sample-and-hold amplifier is not necessary in this type of A/D converter. However, due to the folding operation, the internal frequency in the analog folding preprocessing will be a multiple of the input signal frequency. The result is a limited analog input signal frequency, less than full flash A/D converters achieve. This paper describes an A/D converter architecture in 0.5 /spl mu/m CMOS technology, incorporating a distributed track-and-hold (T/H) operation in the analog folding preprocessing, overcoming the previously-mentioned limitation, Maximum clock frequency is 80 MHz at a power dissipation of 80 mW from a 3.3 V supply voltage. The analog preprocessing reduces the requirements for the differential T/H amplifiers equal to the number of reference operations compared to a single T/H amplifier in front of the A/D converter.

A monolithic wideband variable gain amplifier with a high gain range and low distortion

This variable-gain amplifier has architecture in which the linear input region is inversely proportional to the gain of the circuit. It incorporates a plurality of differential pairs (DP) coupled in parallel, forming a transadmittance stage. The input of each DP is provided with the input signal voltage, shifted by an offset voltage. The offset voltage of each individual DP is variable and independent of other DP offsets. When all offset voltages are equal, the transadmittance stage is set to maximum gain. The linear input region is then comparable to that of a single DP transadmittance stage. When the offset voltages are made equidistant at about 40 to 60 mV, the transadmittance stage is set to minimum gain. The linear input range is then increased compared to the situation of maximum gain and is dependent on the number of DPs. Gain settings between minimum and maximum gain are achieved by values of equidistance of the offset voltages between 0 and 40 to 60 mV. A prototype variable gain amplifier is in a 1 /spl mu/m triple metal bipolar process. It contains 32 parallel DPs and has a differential voltage input as well as output. The gain range is 0 to 25 dB. Active chip area is 0.15 mm/sup 2/. Supply voltage is 5 V and signal bandwidth is about 35 MHz at a power dissipation of 40 mW.