Arnoldus Gerardus Wilhelmus Venes

An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm/sup 2/ in 0.5-/spl mu/m standard digital CMOS technology.

An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing

Successful implementation of folding and interpolation techniques in high-speed A/D converters has been demonstrated in both bipolar and, more recently, CMOS technology. The folding architecture can be considered as a time-continuous two-step architecture. This means that a sample-and-hold amplifier is not necessary in this type of A/D converter. However, due to the folding operation, the internal frequency in the analog folding preprocessing will be a multiple of the input signal frequency. The result is a limited analog input signal frequency, less than full flash A/D converters achieve. This paper describes an A/D converter architecture in 0.5 /spl mu/m CMOS technology, incorporating a distributed track-and-hold (T/H) operation in the analog folding preprocessing, overcoming the previously-mentioned limitation, Maximum clock frequency is 80 MHz at a power dissipation of 80 mW from a 3.3 V supply voltage. The analog preprocessing reduces the requirements for the differential T/H amplifiers equal to the number of reference operations compared to a single T/H amplifier in front of the A/D converter.

A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D Converter

In bipolar technology the folding and interpolation technique has proven to be successful for high sample rates. This paper investigates the possibilities of this technique in CMOS. The major advantage of folding and interpolation in CMOS lies in the field of high sample rate in combination with low power consumption and small chip area. The folding converter requires little power to drive the input compared to other converters since the input behaves like a linear and constant capacitor. For similar reasons the power consumption of the reference ladder of the folding converter can be kept low. The circuit reported here runs at 70 MSample/s and dissipates only 110 mW. There are versions for 5 V and 3.3 V supplies and they are realized in a 0.8 /spl mu/m CMOS process.