R. K. Sharma

Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

The lateral profile of trapped charge in a silicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory programmed using channel-hot-electron injection is determined using current-voltage (I/sub D/-V/sub G/) measurements along with two-dimensional device simulations and is verified using gate-induced-drain-leakage measurements, charge-pumping (CP) measurements, and Monte Carlo simulations. An iterative procedure is used to match simulated I/sub D/-V/sub G/ characteristics with experimental I/sub D/-V/sub G/ characteristics at different stages of programming, by sequentially increasing the trapped electron charge in simulations. Fresh cells are found to contain a high laterally nonuniform trapped charge, which (along with large electron injection during the program) make the conventional CP techniques inadequate for extracting the charge profile. This charge results in a nonmonotonous variation of threshold and flat-band voltages along the channel and makes it impossible to simultaneously determine interface and trapped charge profiles using CP alone. The CP technique is modified for application to SONOS cells and is used to verify the charge profile obtained using I/sub D/-V/sub G/ and to estimate the interface degradation. This paper enhances the study presented in our earlier work.

Sinusoidal Oscillators and Waveform Generators using Modern Electronic Circuit Building Blocks

From the Contents: Introduction -- Op-amp oscillators and waveform generators -- Electronically-Controllable OTA-C oscillators and waveform generators -- Oscillator and waveform generators using Current conveyors.

Investigation of Drain Disturb in SONOS Flash EEPROMs

The mechanism of drain disturb is studied in silicon-oxide-nitride-oxide-silicon Flash electrically erasable programmable read-only memory cells. It is shown that disturb is a serious problem in programmed cells and is caused by injection of hot holes from substrate into the oxide/nitride/oxide stack. The origin of these holes is identified by analyzing the influence of halo doping, channel doping, and channel length scaling on drain disturb. Band-to-band tunneling at the drain junction is normally the dominant source of these holes. It is also shown that holes generated out of impact ionization of channel electrons become dominant in cells with high channel leakage (especially at lower channel lengths). Finally, the effect of repeated program/erase cycling on drain disturb is studied. Drain disturb becomes less severe with cycling, the reasons for which are determined using gate-induced drain leakage measurements and device simulations

A comprehensive trapped charge profiling technique for SONOS flash EEPROMs

Trapped charge profiles under CHE program of SONOS flash cells are uniquely determined and verified using I-V, GIDL and CP measurements and Monte Carlo simulations. The prospect of profiling using I-V measurement alone is discussed. The inaccuracy associated with conventional CP technique is discussed. The correct method of CP simulation for programmed SONOS devices is shown and programming induced interface-trap generation is estimated.

Nullors, Their Bipolar and CMOS Implementations and Applications in Analog Circuit Synthesis and Design

This chapter presents an account of the major developments taken place during the last four decades in the area of nullors, their bipolar and CMOS implementations and applications in modeling of various analog circuit building blocks and synthesis of analog signal processing and signal generation circuits, in a tutorial/review format. It is shown that judicious combinations of these pathological elements, a variety of active elements such as BJT, MOSFET, Op-amp, operational transconductance amplifier (OTA), CCII etc., can be modeled. Novel applications of four terminal floating nullors (FTFN) in analog signal processing and signal generation have been highlighted. Some prominent discrete, bipolar and CMOS implementations of FTFNs, including their fully differential versions, have been reviewed. A novel method of synthesizing analog circuits using nullors advanced by Haigh and his co-workers has been highlighted. Two new pathological elements of more recent origin, namely, the current mirror (CM) and voltage mirror (VM) introduced by Awad and Soliman have been briefly explained. At the end, a brief account of more recent developments and the current trends and the directions/problems for future research in this area have been provided.

Comparative Slope Stability Analysis and Factor of Safety Evaluation of Gambhar Landslide

Geotechnical studies of major landslides that threaten the traffic flow along National Highways are essential for mitigation and to draw a long term plan. There are various methods for analyzing slope stability and the preference was given to simple and logical methods. The type and materials that constitute Gambhar landslide, the choice of adopting Bishop’s simplified method of slices, circular failure charts (CFCs) incorporating varied ground parameters and computer based software GEO5 were used for determining values of factor for safety. The factor of safety derived from three different methods for varied slope conditions indicate that the slopes were critically stable as the factor of safety relating to these slope failures are closer to one. For Gambhar slide, all the adopted methods gave nearly identical values with comparatively lower factor of safety values by CFC method. However, factor of safety values computed by GEO5 are very low indicating very unstable slope even on dry slope condition.