E. Murakami

A New TDDB Degradation Model Based on Cu Ion Drift in Cu Interconnect Dielectrics

A new physical model of time-dependent dielectric breakdown (TDDB) in Cu interconnect dielectrics is proposed. TDDB occurs due to the drift of Cu ions under an electric field E. An activation energy analysis of the leakage current demonstrates that these injected Cu ions affect the conduction mechanism of electrons. The dominant electron conduction mechanism changes from Poole-Frenkel electron current through the Cu barrier dielectrics to Fowler-Nordheim current due to the Cu pile-up at the cathode end. We assumed two possible types of Cu ion drift mechanism, Schottky type or Poole-Frenkel type. The field acceleration model (radicE model) of the Poole-Frenkel type fits both TDDB lifetime and activation energy very well. The TDDB lifetime is proportional to the exponential of the square root of the electric field radicE

Modeling of NBTI degradation and its impact on electric field dependence of the lifetime

Negative Bias Temperature Instability of p-MOSFETs is investigated under various stress gate voltages and temperatures. It is shown that degradation tends to saturate and the dependence of lifetime on electric field (Eox) is expressed as a power-law of Eox. We propose new empirical and kinetic models. The Eox dependence of the lifetime described by the power-law is derived from our empirical model describing the saturation of degradation. Moreover, our kinetic model explains the saturation behavior.

Modeling of NBTI saturation effect and its impact on electric field dependence of the lifetime

Abstract Negative Bias Temperature Instability of pMOSFETs is investigated under various stress gate voltages and temperatures. It is shown that degradation tends to saturate and the dependence of lifetime on electric field (Eox) is expressed as a power-law of Eox. We propose new empirical and kinetic models. The Eox dependence of the lifetime described by the power-law is derived from our empirical model describing the saturation of degradation. Moreover, our kinetic model explains the saturation behavior.

Universality of power-law voltage dependence for TDDB lifetime in thin gate oxide PMOSFETs

Voltage, polarity and thickness dependencies of time-to breakdown in n-FETs and p-FETs are investigated under inversion and accumulation conditions. The voltage dependence of all the cases is clearly described by a power-law. The voltage acceleration exponents (n) of the power-law of 45 (n-FETs inv.), 40 (n-FETs acc.) and 44 (p-FETs acc.) are independent of thickness. On the other hand, in p-FETs under inversion mode, the exponents (n) are /spl sim/45 for |Vg|>3.8 V and 33 for |Vg|<3.8 V, regardless of thickness. This change in the exponent (n) is explained by a cathode side hydrogen release model.

A study of SRAM NBTI by OTF measurement

A mechanism of DeltaVth variation of NBTI for SRAM load transistor is examined. The variation data is in good agreement with our proposed model. A large fluctuation of NBTI for small size pMOS is not observed in HCI measurement for nMOS, which may be due to the difference of recovery. Two types of equations to get DeltaVth from DeltaIdL by OTF measurement are compared and we have concluded which equation is appropriate by using pulse IV method. We have also proposed a new method to predict precise median value of NBTI for SRAM by OTF measurement with parallel TEG. This method is very important to design initial Vth region of SRAM.

Electric-field and temperature dependencies of TDDB degradation in Cu/Low-K damascene structures

The electric field and temperature dependencies of time-dependent dielectric breakdown (TDDB) degradation in Cu/low-k damascene structures are investigated using Cu/SiOC and Cu/SiCN damascene structures. A field-dependent activation energy analysis of TDDB lifetimes demonstrates that there are multiple TDDB degradation mechanisms for a Cu/SiOC structure and that the dominant TDDB degradation mechanism is dependent on the electric field. Under higher electric fields, the SiCN film used as a Cu barrier dielectric (BD) is the main cause of the TDDB failure. As the electric field decreases, the degradation of the inter-level dielectric (ILD) or ILD/BD interface has an impact on TDDB failure. Furthermore, it was found that the field-dependency of Ea reflects the dominant TDDB degradation mechanism and is an important factor in determining a TDDB degradation model that can predict an accurate TDDB lifetime.

NBT-induced hot carrier (HC) effect: positive feedback mechanism in p-MOSFET's degradation

We demonstrate a new mode of Hot-Carrier (HC) degradation of p-MOSFETs. A positive feedback HC degradation caused by positive fixed oxide charge increasing the electric field at the drain edge is observed. When TTL AC stress (HC and NBT stress one after another) is applied, this degradation is enhanced. It is assumed that NBT stress produces positive fixed oxide charges easily (NBT-induced HC degradation). It is also shown that this new degradation can be suppressed by halo design.

Neutron-induced soft error in logic devices using quasi-monoenergetic neutron beam

The neutron-induced soft error in logic devices was investigated using a quasi-monoenergetic neutron beam. The SER of the flip-flop circuit is approximately 1/3/spl sim/1/5, that of the embedded SRAM per bit. Taking into account the increasing circuit scale, SER of logic circuit can no longer be ignored. As the node charge of the cell becomes less than 6fC, the SER mainly occurs due to the light particles generated by a nuclear reaction between neutrons and Si nuclei. We propose a method of SER estimation for various embedded SRAMs and data-latch circuits with various layout designs in logic devices using the SER normalized by the n+ diffusion area of the memory node.

Modeling of Cu IMD-TDDB caused by extrinsic defects

In this paper, a prediction method for degradation failure ratio (B-mode) of Cu IMD-TDDB is studied. In this study, B-mode failure is assumed to be caused by dielectric thinning due to random defects (thinning model). Its probability is calculated by Critical Area Analysis (CAA). Prediction is in good agreement with measurement results. This method can be applied to estimate reliability of various LSI products.

Study of formation mechanism of nickel silicide discontinuities in high performance CMOS devices

We performed detailed analysis of Ni silicide discontinuities induced by agglomeration that causes the increasing electric resistance in high-performance CMOS devices by using advanced physical analysis techniques. We confirmed that the agglomeration of the Ni silicide is related to elongated-triangular- shaped-splits — which we call delta-shaped-splits — which cause discontinuities that occur at small-angle grain boundaries pinned by boron clusters even with small stress. We successfully determined the formation mechanism of the Ni silicide discontinuities in detail. It is essential to develop a highly reliable Ni salicide process, especially for 45 nm node high performance devices and beyond.