R. Koga

Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs

Cosmic ray interactions with memory cells are known to cause temporary, random, bit errors in some designs. The sensitivity of polysilicon gate CMOS static RAM designs to logic upset by impinging ions has been studied using computer simulations and experimental heavy ion bombardment. Results of the simulations are confirmed by experimental upset cross-section data. Analytical models have been extended to determine and evaluate design modifications which reduce memory cell sensitivity to cosmic ions. A simple design modification, the addition of decoupling resistance in the feedback path, is shown to produce static RAMs immune to cosmic ray-induced bit errors.

Techniques of Microprocessor Testing and SEU-Rate Prediction

Several different approaches have been used in the past to assess the vulnerability of microprocessors to SEU. In this paper we discuss the advantages and disadvantages of each of these test methods, and address the question of how the microprocessor test results can be used to estimate upset rate in space. Finally, as an application of the above techniques, we present the test results and predicted upset rates in synchronous orbit for a selected group of microprocessors.

Heavy Ion-Induced Single Event Upsets of Microcircuits; A Summary of the Aerospace Corporation Test Data

A summary of heavy ion SEU and latch-up data collected within the last several years is presented in this report. The devices tested range from simple logic circuits to microprocessors including examples of bipolar, CMOS, and NMOS technologies.

The Effect of Elevated Temperature on Latchup and Bit Errors in CMOS Devices

Equipment for testing microcircuits at elevated temperatures for Single Event Phenomena (SEP) such as upset (SEU) and latchup (SEL) has been developed and measurements on several device types have been performed. Very large changes in cross-section and threshold LET have been observed over the temperature range of 25°C to 120°C for SEU and SEL.

Heavy Ion Induced Upsets in Semiconductor Devices

Heavy ions produced at various accelerator facilities have been employed to measure the effect of cosmic rays on semiconductor devices in space. An ion transmission counter, a solid state detector, and a position sensitive detector comprise the beam-monitor system used to measure the flux in real time and to monitor the spatial beam uniformity. An LSI 11/23 computer exercises the semiconductor devices under test. The technique of the experiment especially involving ever increasing complexity of dévices will be described along with the upset results obtained from some devices.

SEU Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors

A detailed analysis of the SEU vulnerability of the Zilog Z-80 microprocessor is presented based upon data obtained with heavy ions and protons. The analysis demonstrates a method for separating upsets of the general purpose registers from upsets of the internal latches. Furthermore, the analysis shows that the bulk of the upsets observed below a LET value of 4 Mev-cmsq/mg is associated with upset of these internal latches. To obtain the data which made this analysis possible, a novel test technique was developed which associates all upsets with the machine cycle during which they first appear on the device pins. Limited data for the NSC-800 are included.

Soft Error Susceptibility of CMOS RAMS: Dependence upon Power Supply Voltage

Two types of a delidded CMOS 1024 × 1 RAM (Harris HM 6508-RH and Sandia TA597) have been tested for susceptibility to soft bit errors caused by 150-MeV krypton ions. Bit-error susceptibility was measured as a function of bias voltage and ion beam angle with respect to the chip-face normal. Comparison of measured bit-error rates and thresholds with those computed by use of a simple device model and manufacturer-supplied data shows good agreement in some respects while raising questions in others. In the case of the HM 6508-RH RAMs, measured values of critical charge of 1 pC and 2 pC at 5V and 7V, respectively, indicate that the devices can be expected to 4show bit-error rates in space of approximately 1 × 10-4 per chip per day at 5V bias and 1 × 10-5 per chip per day at 7V bias.

Effects of Heavy Ions on Microcircuits in Space: Recently Investigated Upset Mechanisms

Upsets of microcircuits in space have been attributed to heavy ions. In recent studies of the failure mechanisms, we have employed a wide range of test methods. These studies and the application of the test results to space borne microcircuits are presented.

Bevalac ion beam characterizations for single event phenomena

Linear Energy Transfer (LET) distributions of Bevalac ion beams were measured. Subsequent analysis has called into question the standard assumption of a monoenergetic, single-species beam at Bevalac. Both high LET contaminants in the primary beam and very broad LET peaks in degraded beams were observed. High energy ion beams at other accelerators may possess similar characteristics. The existence of beam impurities may have important ramifications for the interpretation of single-event phenomena observed at high energy accelerator sites.

Single Event Upset Vulnerability of Selected 4K and 16K CMOS Static RAM's

Measurements of single event upset probability for several types of prototype bulk CMOS and CMOS/SOS RAMs have been made using beams of 140 MeV krypton, 160 MeV argon and 33 MeV oxygen ions from the Lawrence Berkeley Laboratory 88-in cyclotron. Upset thresholds, determined by varying the ion species and beam-incidence angles, were used in conjunction with manufacturer-supplied information on device design parameters to estimate values of critical charge for upset. These experimental values are in reasonably good agreement with scaling predictions of Petersen et al. and Pickel. Comparison of the critical charge values deduced from experiment with predictions obtained for the 16K CMOS/SOS devices by means of SPICE and RCAP simulation codes shows discrepancies of approximately a factor of two. These discrepancies indicate the need of additional experimental and theoretical work before an adequate understanding of device response to charged particle bombardment is achieved.