S. E. Diehl

Suggested Single Event Upset Figure of Merit

This paper examines a number of concepts that are connected, directly or indirectly, with the problem of assigning a single event upset figure of merit to a specific oevice. Single event rates depend both on device and circuitry, through the critical charge requisite for upset, and upon the device geometry and technology, which determine the target size and charge collection capability. Each of these factors must be taken into account when determining device susceptibility. Upset rates in space additionally depend on the environment. Device response in trapped proton belts and in the cosmic ray environment is sufficiently oifferent that a single susceptibility measure is inadequate. We conclude that devices should be characterizea by a proton susceptibility, and by an upset rate in a reference cosmic ray environment. We present a simple expression, based on laboratory measurement, that approximates the cosmic ray upset rate ano propose it as a figure of merit. Calculated and measured values for upset rates are sensitive to several factors. The field funneling effect is known to increase both the magnitude of collected charge and the effective sensitive circuit volume during single events relative to the static parameters. Thus, experimental sensitive area measurements obtained from single event data exceed values predicted from inspection of static circuit layout configurations. Also, more charge is collected from any specific event than is predicted by using depletion region extent to determine charge collection volumes. This effect must be included when critical upset charge values are determined from experimental upset thresholds.

Single Event Error Immune CMOS RAM

A technique involving resistive decoupling has been developed and applied to the memory cells of a 1024-bit CMOS static RAM to provide immunity to single event upset by cosmic rays. Doped polysilicon resistors were inserted in the inverter-pair cross-coupling lines of an existing memory-cell design with negligible effect on the device operating characteristics. Computer simulations, as well as laboratory tests with energetic krypton ions, imply the effectiveness of this approach to solving the single event upset problem in satellites. This technique is expected to be applicable to other devices of this type, including those with higher levels of integration.

Considerations for Single Event Immune VLSI Logic

The applicability of resistive decoupling and other hardening techniques to circuits and chip level systems at very large scales of integration and at very high signal speeds is considered. Circuits may sustain soft errors due to ion interactions with non-RAM logic. The modes of ion-induced error production in non-memory circuitry are identified and methods of upset reduction or prevention determined to produce single event immune circuit designs. The applicability of hardening methods to logic of smaller size and/or higher speed is identified. Established computer simulation methods are used to predict limitations for single event immune integrated circuits. The single event problem is defined and characterized at a chip level, and criteria are suggested for optimizing designs for use in ion environments. (LEW)

An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMS

A technique that will improve RAM cell performance while maintaining single event upset immunity has been identified. The resistor-hardening configuration combines cross-coupled gate resistors and a pair of resistors used to isolate the miore sensitive devices (those not fabricated in wells). Improvements in RAM cell write time and critical charge are discussed as well as the impact of this technique on the cells noise miargin.

Dose-Rate Upset Patterns in a 16K CMOS SRAM

Dose-rate LINAC tests have been performed on the Sandia National Laboratories SA3240 16k CMOS SRAM and transient radiation induced upset patterns are presented. These patterns indicate a progression of upsets across the memory array with increasing doserate, as predicted by computer simulations of the rail span collapse effect. The upset bitmap patterns and simulation results show that VDD power supply bussing is not critical, or even necessary, for radiation hardened CMOS epitaxial parts if local VDD taps to a powered substrate are used; the critical factor is the efficiency of the VSS bussing scheme. The effects of initial storage patterns and total ionizing dose on the upset patterns are also presented.

Simulation of Worst-Case Total Dose Radiation Effects in CMOS VLSI Circuits

A new methodology for evaluating worst-case radiation failure levels for CMOS VLSI circuits in total dose environments is presented. The new methodology reduces computation time by orders of magnitude by using simple calculations to identify vulnerable sub-circuits and worst-case irradiation and operating bias conditions. Sensitive sub-circuits are then analyzed by accurate, device-level simulators to predict radiation failure levels. The method has been implemented and results for sample circuits are described.

Analytic Expressions for the Critical Charge in CMOS Static RAM Cells

Common trajectories associated with logic state reversal are discussed, and an analytical expression is developed for the critical charge required for single event upset of CMOS static RAMs.

Comparisons of Single Event Vulnerability of GaAs SRAMS

A GaAs MESFET/JFET model incorporated into SPICE has been used to accurately describe C-EJFET, E/D MESFET and D MESFET/resistor GaAs memory technologies. These cells have been evaluated for critical charges due to gate-to-drain and drain-to-source charge collection. Low gate-to-drain critical charges limit conventional GaAs SRAM soft error rates to approximately 1E-6 errors/bit-day. SEU hardening approaches including decoupling resistors, diodes, and FETs have been investigated. Results predict GaAs RAM cell critical charges can be increased to over 0.1pC. Soft error rates in such hardened memories may approach 1E-7 errors/bit-day without significantly reducing memory speed. Tradeoffs between hardening level, performance and fabrication complexity are discussed.

Factors Contributing to Cmos Static Ram Upset

Phenomena contributing to transient radiation induced static RAM (SRAM) cell upset in CMOS integrated circuits (ICs) include rail span collapse, dynamic FET threshold voltage shifts, photocurrents internal to the RAM cell, secondary photocurrents, and lateral variations in silicon surface potential. Of these phenomena, it is found that the major contributors are rail span collapse and internal cell photocurrents. A model is presented which combines global rail span collapse calculations with detailed analyses of local effects in the ram cell.

A Model of Transient Radiation Effects in GaAs Static RAM Cells

A model to simulate the effects of transient radiation in GaAs static RAM cells has been developed. It accounts for radiation currents through bulk photocurrents and channel conductivity modulation. The model explains upset effects unique to GaAs SRAMs and the results agree with recent experimental data.