R. Loo

Color-sensitive photodetector based on porous silicon superlattices

Color-sensitivity of Si photodiodes was achieved by integrating porous silicon (PS) Bragg reflectors and Fabry–Perot filters. The PS was formed in the p+-type part of the p+n junction which required illumination of the samples during anodization. The optimal illumination power density turned out to be a compromise: high power densities are necessary to enable high anodization current densities, but this results in a degraded filter performance. The PS layers had no significant influence on the electrical characteristics of the photodiodes, but as expected they strongly modified the spectral response. The results are in good agreement with the reflectance spectra of the filters.

Color-Sensitive Si-Photodiode Using Porous Silicon Interference Filters

A new method for the fabrication of color-sensitive Si-photodiodes is presented. Color sensitivity was achieved by using porous silicon multilayer stacks which act as interference filters if the formation parameters are controlled carefully. These filters were integrated in the upper, p+-type part of a p+n-junction. As expected, the spectral response of the photodiodes was determined by the transmission spectra of the filters, while the porous silicon had no significant influence on the electrical characteristics. The great advantage of this method over conventional ones is that it makes very cheap, fast filter fabrication requiring no expensive deposition process possible.

Photoluminescence and transmission electron microscopy investigation of SiGe quantum wires grown on patterned Si substrates

Abstract Growth of SiGe by low pressure chemical vapor deposition on nonplanar Si substrates is studied for nominal Ge concentrations of 0.4 ≤xGenom.≤1. Self-organized growth leads to the formation of approx. 30 nm wide SiGe quantum wires at convex corners of the substrate. In photoluminescence (PL) spectra of samples with xGenom. = 0.4 we identify transitions from quantum wells on the flat parts of the substrate and from quantum wires. The energetic positions of the quantum wire transitions are in good agreement with Ge concentrations measured by spatially resolved energy dispersive X-ray spectroscopy, using a scanning transmission electron microscope (TEM). We find that the Ge concentration inside the wire is considerably lower than the nominal value for growth on planar parts of the substrate. Even for wires grown with xGenom. = 1, where only GeH4 and H2 are present during growth, PL and TEM indicate a Ge concentration as low as 32% for the wires. In such growth experiments we observe different regimes of strain relaxation. While quantum wires and wells are heavily decorated with Stranski-Krastanov islands in larger structures, smaller structures (≤5 μm) exhibit homogeneous thickness.

Vertical Si p-MOS transistor selectively grown by low pressure chemical vapour deposition

Abstract Low pressure chemical vapour deposition was used to define the channel length of vertical Si p-MOS transistors. Comparing to a conventional lateral transistor, the vertical structure is expected to enhance the packing density. The growth technique permits an easy reduction of the channel length without complex technological preparation steps. Besides, it allows a selective deposition in which facet growth occurs, which in turn leads to a thinner channel length compared to the distance between the two pn-junctions in the volume area. Therefore, the facet growth leads to a shift of the punch-through effect to higher voltages. Device characteristics of a non-optimized transistor geometry, on which the gate oxide is prepared after the epitaxial growth, with a channel length of approximately 250 nm and a gate oxide thickness of 12 nm, show a transconductance of 70 mS mm−1, an ideal sub-threshold behaviour of 100 mV dec−1, an off-current below 10−12 A μm−2 and a breakthrough voltage |VD|>4 V. Devices with a preparation of the gate oxide before epitaxial growth have also been studied. These devices show a transconductance of 25 mS mm−1 for a gate oxide thickness of 40 nm.

Vertical 100 nm Si-p channel JFET grown by selective epitaxy

Abstract We have fabricated a vertical silicon junction field-effect transistor (JFET) with a SiO 2 /polysilicon/SiO 2 gate structure. Due to the vertical structure the polysilicon gate length can be easily controlled in the sub-100 nm region. The SiO 2 layers below and above the gate reduce the gate-drain and gate-source capacitance due to the relatively low dielectric constant of the SiO 2 . In addition the SiO 2 above the gate structure allows the use of selective epitaxy. The channel length of the devices was varied from 0.6 μm down to 0.3 μm leading to an improvement of the transconductance and output conductance. A transconductance of 51 mS/mm was achieved for a channel length of 0.4 μm.

Intense photoluminescence from strained SiGe sub-100 nm wires selectively grown on Si by LPCVD

Abstract Selective epitaxial growth by low pressure chemical vapor deposition has been used to produce SiGe-heterostructures in oxide-windows parallel to 〈110〉 or 〈100〉 directions on (001) silicon substrates. For 〈110〉 oxide-wall directions, {111} and {311} facets are formed at the edge of the epitaxial areas, while only {110} facets develop for 〈100〉 directions. Transmission electron microscopy characterizations have clearly shown the formation of quantum wires near the intersecting (001) and {110} planes. The wires have a regular width of 100 nm and a thickness of 6 nm and show a very strong photoluminescence.