R.M. Warner

Channel-collector transistors

By merging the channel regions of two-junction field-effect transistors with the collector region of a bipolar junction transistor (BJT), one achieves a quasi-cascode configuration called a Channel-Collector Transistor (CCT). Its terminal properties are those of a modified, improved bipolar transistor. Prototype devices have been fabricated with common-emitter current gain (βF) in excess of 1200 while still maintaining the common-emitter, open-base breakdown voltage (BVCE0) greater than 140 V and the output resistance r0typically greater than 200 kΩ. The present brief describes an efficient, qualitative equivalent circuit for the structure and also presents an experimental device graphically illustrating the CCTs advantages and disadvantages when compared to a conventional BJT.

Modeling the transition region of a symmetric step junction

The authors are indebted to Dr.B.L.Grung for several helpful suggestions concerning this paper.

A general solution for step junctions with infinite extrinsic end regions at equilibrium

We present here a unified solution to determine the potential profiles for step junctions in equilibrium. The complete solution is determined by solving for the two sides of the junction separately. The generalized solution consists first of a curve corresponding to majority-carrier accumulation, i.e, the low side of high-low junction. Second, it consists of a family of curves corresponding to majority-carrier depletion, i.e., the high side of a high-low junction and either side of a p-n junction. The curves in the latter case approach a common asymptote that by itself constitutes a solution for all but lightly doped sides of asymmetric p-n junctions.

A note on IC-yield statistics

Abstract Expressions given by Moore and by Dingwall for relating integrated-circuit yield to area are compared and are given a common interpretation in terms of the composite model. The issue of large-chip yield projection is discussed, a subject that is still unclear because of the concave-up projections of the empirical curves, the linear projection of the composite model, and the concave-down projections of recent analytical models.

An analytical model for the epitaxial bipolar transistor

In the n+pn−n+ transistor, high-current effects in the base and collector regions are linked within the current ranges of practical interest. To describe such effects, we have derived an analytical model that is based primarily on five assumptions: (1) the structure is approximately one-dimensional; (2) recombination is negligible in the base and collector quasi-neutral regions, and in the three space-charge regions; (3) high-current effects are negligible in the emitter and n+-substrate regions; (4) the Fletcher boundary conditions (or the Misawa boundary conditions) can be used for the three space-charge regions; and (5) the ambipolar approach can be used for the base and collector quasi-neutral regions. The primary findings predicted by the n+pn−n+ transistor model are: In current ranges of practical interest (usable current gain), the electron concentration profile has a significant “vertical step” located at the collector-base metallurgical junction for all values of collector current. In the limit of extremely-high-current operation, this step tends to vanish. In the current range where the current gain begins to decline rapidly with increasing collector current, the electron concentration at the base boundary of the collector-base space-charge region goes approximately as the square of the hole concentration at the collector boundary of the same region. Because of this relationship, a charge-control calculation is more difficult than a straightforward calculation of carrier concentration for a given degree of accuracy. The n+pn−n+ transistor model (which consists of twelve algebraic equations) is particularly useful for the practically important case of an epitaxial bipolar transistor having a very thin, heavily-doped base region.

A new scaling length for modeling semiconductor space-charge regions

Intrinsic and extrinsic Debye lengths have been extensively used in device modeling work. Recently Jindal and Warner [4], using extrinsic Debye length, have developed a unified solution applicable to all step junctions. They have further extended it to include the semiconductor surface problem [5]. As a result of these general analyses, the role of extrinsic Debye length in distance normalization in cases where mobile charges are dominant has been more clearly understood. A new scaling length, whose use is complementary to that of extrinsic Debye length is proposed for cases where fixed charge is dominant.

Field and related semiconductor-surface and equilibrium-step-junction variables in terms of the general solution

A depletion-approximation replacement offered recently employs one of two asymptotic functions of a universal curve of potential versus position to define a spatial origin, which is then used to write approximate-analytic expressions of simple form for the universal curve. Here we extend analogous treatment to additional functions, writing expressions as a function of normalized potential and of normalized position.

Modeling the inversion layer at equilibrium

Abstract Recent developments in the modeling of a step junction or a semiconductor surface at equilibrium have yielded a set of approximate-analytic expressions that relate normalized potential to normalized position outside the inversion regime. Here we offer analogous approximate-analytic expressions for the relations between normalized potential, normalized position and normalized electric field within the inversion regime, for a range of variables of practical interest. A real charge density in the inversion layer obtained analytically using these expressions is compared with the value obtained from the charge-sheet model of Brews, and is shown to be appreciably more accurate.

Electron-velocity saturation at a BJT collector junction under low-level conditions

The consequences of electron-velocity saturation at the collector junction of an n-p-n biopolar junction transistor (BJT) are examined in a manner similar to that employed by Middlebrook twenty years ago. Dimensional shrinkage, especially in base thickness, that has occurred over this time interval causes a change in the prediction of this analysis from a negligible effect twenty years ago to a significant effect today, even in the low-level regime. However, a more detailed analysis considering the electron profile near the collector junction yields the somewhat surprising result that the linear portion of the base-region electron profile is quite unaffected by velocity saturation, in spite of the fact that the minimum electron density ncin the collector region can exceed by many orders of magnitude the equilibrium electron density in the base region. The reason for this is a scaling phenomenon wherein the linear-profile extrapolation rotates about a point on the x axis that is invariant with respect to current throughout the low-level range and approximately invariant with respect to base-region doping. Furthermore, this point on thexaxis is very close to the depletion-approximation boundary of the collector-junction space-charge layer. Hence, the classical assumption of vanishing electron density at the boundary of the collector space-charge region constitutes an excellent approximation for low-level conditions. Incidental to the detailed analysis are updated empirical expressions for electron velocity saturation, and an application of the general solution for step junctions that was offered recently.

A bipolar lock-layer transistor

Abstract A bipolar transistor and a junction field effect transistor are integrated into a “merged” cascode configuration. Viewed as a modified bipolar transistor, this device has a new and favorable combination of common-emitter breakdown voltage and current gain, and is largely free of the Early effect .