R. Nagulapalli

A CMOS technology friendly wider bandwidth opamp frequency compensation

In this a paper a novel CMOS technology friendly opamp compensation has been presented and explained intuitively miller compensation pole splitting. Present technique utilizes grounded capacitor and having better PSRR. Open loop transfer functions have been derived to show the proposed technique is low power for the same bandwidth. Implemented in 65nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed opamp achieves FOM ∼83333.Opamp consumes 25uA from 1V supply and occupying 5184um2 silicon area.

A Start-up Assisted Fully Differential Folded Cascode Opamp

This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing ...

A compact high gain opamp for Bio-medical appli-cations in 45nm CMOStechnology

In this paper a low OpAmp compensation technique suitable for the bio-medical application has been proposed and intuitive explained the existing compensation techniques. The Present technique relies on the passive damping factor control rather power hungry damping. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that 100dB dc gain, well compensated 25MHz bandwidth OpAmp while driving a 1pF capacitive load. Draws with 12uW power consumption from 1V supply and occupying 0.004875mm2 silicon areas.

A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm2, and at room temperature, it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from −40∘C to 125∘C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/∘C.

A novel current reference in 45nm cmos technology

In this paper a novel CMOS temperature and supply voltage independent current reference has been proposed. This design is based on subtraction of two scaled version PTAT (proportional to temperature) currents to get temperature independent current reference. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed current reference achieves temperature coefficient of 22ppm/°C against temperature variation of −4O°C–120°C and line sensitivity of 337ppm/V against supply variation of 0.6–1.8V, while consuming 135uW from 1.8V supply and occupying 5184um2.

A Microwatt Low Voltage Bandgap Reference for Bio-medical Applications

In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.