R. Pagano

Parallel strings of IGBTs in short circuit transients: analysis of the parameter influence and experimental behavior

In this paper the behavior analysis of parallel connection of IGBTs under short circuit conditions is presented. The issues of hard switching fault (HSF) and fault under load (FUL) short circuit types are faced by taking into account for the influence of the layout and gate driving parameters. The role of the temperature has been considered too in order to investigate how this quantity affects the IGBTs short circuit phenomenon. An analytical description of the FUL transient is introduced to put in correlation the current and voltage peaks, which are suffered by the IGBT, to the circuit and device parameters. Indeed, the current peak imbalance appearing in a FUL condition is depending on the power layout, on the gate driving conditions and spread on device parameters.

A novel protection technique devoted to the improvement of the short circuit ruggedness of IGBTs

This paper deals with a novel short circuit protection technique that is applied during fault under load (FUL) conditions occurring on IGBT devices. An experimental analysis of rugged IGBTs, which are submitted to FUL transients, has been performed dwelling upon the main stresses associated with the fault. In particular, the issues pertinent to the current transient are analysed, and the state-of-the-art regarding the protection circuit as appearing in literature is recalled and discussed. A novel circuitry is proposed aiming to strongly limit the peak of current deriving from a FUL transient, thus limiting the considerable energetic and thermal stresses onto the device. Besides, a theoretical analysis explaining the working mechanism of the proposed circuit has been carried out. Finally, the experimental results, which have been obtained by exploiting a suitable breadboard able to create FUL transients, confirm the validity and correctness of the proposed approach.

Driving a New Monolithic Cascode Device in a DC–DC Converter Application

In this paper, a case study application of a new device, which is based on a bipolar-MOSFET cascode connection, is presented. The monolithic device can be designed for high-voltage applications up to 1.7-2.2 kV. The basic features of this power device are described in terms of the physical structure and the electrical performance. An application in the field of dc-dc converters is presented, and the drive unit requirements are investigated and discussed through several circuit topologies that are devoted to energizing the four-terminal device. The advantages and the drawbacks of the device are compared with those of a MOSFET in terms of the switching losses and the command circuitry. The correlation between the physical structure of the cascode and its electrical characteristics is explained to better understand some interesting features of the device. Last, the new device is tested by using a forward converter as a workbench to provide converter designers with useful guidelines concerning the switching behavior and the power losses.

Analysis and performances of a new emitter-switching bipolar transistor device suitable for high-voltage applications

This paper deals with the analysis and experimental investigation of a new monolithic cascode, named the emitter-switching bipolar transistor (ESBT), which is suitable for high-voltage medium-frequency applications. The performances of the device are compared with those of a power MOSFET, having equal blocking voltage and equal rated current. The experimental investigation has been carried out in an actual application using a flyback scheme as workbench. The main advantages and drawbacks of the two devices, with special reference to the switching characteristics and the forward voltage, are hence shown, thus providing useful information to the power converter designers looking for a good exploiting of the ESBT. The correlation between the physical structure of the ESBT and its electrical characteristics is explained aiming to understand some interesting features belonging to the device family. Finally, analysis and discussion on the ESBT driving requirements are done, while several circuit topologies, which are devoted to energize the four-terminal device, are proposed.

Evolution in IGBT's protection against short circuit behaviors by gate-side circuitry

Some strategies of protection against short-circuit faults, which are able to limit the current through IGBT devices, are discussed in this project. A preliminary description of the fault types hard switching fault (HSF) and fault under load (FUL) is presented along with known protection mechanisms intended to reduce the negative effects on the integrity of the devices. The damages induced by a fault condition can be prevented by means of a suitable gate-side circuitry designed to this aim, thus allowing safe operation of the IGBTs. The goal of this protection circuit is not only to avoid the device failure but also eventually assuring the recovery of the conducting state as long as the fault causes expire. Besides, the intervention to impede high current peak transients, though not leading to failure, is requested in order to decrease the thermal stresses on the devices. An alternative different way, aiming to approach the short circuit protection issue, is obtained by the integration of both the gate-side circuitry and the power device in a monolithic chip for the sake of providing within the IGBT the diagnostic and the protection functions too. Such a solution, which is briefly recalled with reference to the state of the art, is to compared with the new one.

Analysis modeling and simulation of low-voltage MOSFETs in synchronous-rectifier buck-converter applications

Nowadays voltage regulator modules (VRMs) are high switching frequency applications devoted to supply low-voltage and high current with more and more increasing slew rates. Excellent performances can be provided by using a synchronous-rectifier buck converter, which allows overcoming the limitations in terms of efficiency shown by a standard buck topology with Schottky diode. A proper design of the synchronous-rectifier is fundamental to obtain the desired performance from the converter due to its considerable contribute to the total power losses. In this paper analysis modeling and simulation of low-voltage power MOSFETs in synchronous-rectifier buck-converter applications are reported. The MOSFET model has been derived by using an advanced process simulator, which represents the device as a two-dimensional (2-D) finite-element grid. Structure parameters have been derived from flow-chart data pertaining to the MOSFET fabrication, which have been optimised by comparing measured and simulated electrical characteristics. Static and dynamic behaviors relative to the studied device have been simulated through a 2-D mixed device and circuit simulator, and used to extract the structure parameters till to obtain a good match with the experimental results. A synchronous-rectifier buck-converter application has been experimentally analysed by arranging a suitable breadboard, in which the same device type has been used for both the high-side and low-side switch. Simulation runs, performed by implementing a behavioral model of the MOSFET device, have been reported too.

Efficiency Improvement of Synchronous Buck Converter by Integrated Schottky Diode in Low-Voltage MOSFETs

This paper deals with the performance evaluation of low-voltage power MOSFETs having integrated Schottky diodes into the same die. The combined MOSFET-Schottky diode structure has been realized in order to improve both the efficiency and the performances of low power synchronous-rectifier buck converters in the field of mobile applications. The main technology issues are shortly recalled and the focus is on the innovations and the advantages deriving from the new device. The behavior in DC-DC converters such as Voltage Regulator Modules (VRMs) has been evaluated in order to give evidence to the significant improvements that may be achieved by using combined MOSFET-Schottky diode structure. The DC-DC converter efficiency improvement has been evaluated by comparing the single chip device performances with a standard MOSFET in VRM applications.

Efficiency modeling of wireless power transfer ASICs accounting for layout parasitics

This paper presents a power-loss model for Lateral- Diffused MOSFETs (LDMOSs) in application-specific integrated circuits (ASICs) in the field of wireless power-transfer system applications. Both the transmitter and receiver power-stages integrated in their respective ASIC units were considered, and the total system efficiency was subsequently estimated. Layout parasitics pertaining to the primary and secondary integrated circuits (ICs) have been considered due to their impact on the total system efficiency, and a charge-sheet control model for the LDMOSs of the three power stages has been developed. Thermal effects induced by heating within the two ASICs were also included, as they exert a significant influence on the amount of both conduction and switching losses. Model results and experimental data are compared and show a satisfactory agreement.

Efficiency optimization of an integrated wireless power transfer system by a genetic algorithm

This paper presents a multi-objective genetic algorithm (GA) for a wireless power transfer system composed of a full-bridge series-resonant inverter (FBSRI), a synchronous full-bridge rectifier (SFBR) and a buck converter. The proposed algorithm maximizes the total system efficiency by optimizing the switching frequency of the FBSRI and the SFBR output voltage, subject to their respective design constraints. Two application-specific integrated circuits (ASICs) respectively integrating the transmitter and receiver power-stages along with their controllers were optimized by the new algorithm. A discrete-time small-signal model of the system has been developed to analyze the stability of the wireless charger. Experimental results validating the above analysis are reported along with simulation data. The wireless power transfer system analyzed in this paper conforms to Wireless Power Consortium (WPC) specifications.

Modeling of planar coils for wireless power transfer systems including substrate effects

This paper presents an analytical model of the impedance between two coils supported by ferrite shield. The new model is not restricted to round coils and applies to more complex winding geometries, as specified by the Wireless Power Consortium. The mutual inductance is derived by solving Maxwells equations and using Bessel function of the first kind. The model results are compared with experimental data as a function of the vertical displacement between the coils. In addition, a wireless power transfer system is modeled to calculate system efficiency by adopting the above coils impedance model. Experimental results run on 5W wireless power transfer system at several displacement steps are compared against simulation data.