R. Piagge

Determination of density profile of ultrathin SiO2/Si3N4/SiO2/Si(001) multilayer structures using x-ray reflectivity technique

In this report, we present an analysis of a SiO2/Si3N4/SiO2/Si(001) ultrathin multilayer structure using the x-ray reflectivity technique. The trilayer was grown using low-pressure chemical vapor deposition with each layer having a nominal thickness of ∼50 A. Here, we propose an approach to analyze ultrathin multilayer films using two analysis schemes in tandem, i.e., distorted wave Born approximation and exact recursive formalism for x-ray reflectivity. We observe that, when SiO2 is deposited on a Si substrate, the electron density is lower than when it is deposited on Si3N4. We also observe that the two interfaces of the nitride (Si3N4) film are different, i.e., the interfacial width with the lower SiO2 is larger than the width with the top SiO2 layer.

High-K dielectrics for inter-poly application in non volatile memories

Abstract Aim of this work is to investigate the conduction characteristics of different high-K dielectrics deposited by ALD technique. A novel methodology which allows the evaluation of very low leakage current at least two-orders lower than standard I – V characteristics with a reduced 3-masks process flow has been used. A comparison with standard ONO technology is performed and shows that the Al 2 O 3 layer is the most promising candidate for ONO replacement. Different techniques for depositing this layer have been compared investigating the impact of subsequent thermal treatments, which greatly improve Al 2 O 3 performances.

Charge retention phenomena in CT silicon nitride: Impact of technology and operating conditions

The aim of this work is to understand charge loss mechanisms in TANOS stack for which charge retention is monitored just after programming in an almost continuous way and voltage is applied during retention experiments in order to obtain zero electric field either on alumina or tunnel oxide. The charge loss mechanisms in TANOS stack can be a quite complicated process: An initial fast DT from interface traps localized at SiN/alumina interface, followed by charge loss through alumina from bulk traps in SiN which influences charge redistribution towards the tunnel oxide, observed only in Si-rich SiN. Programming voltage and stack composition impact trapped charge localization and hence charge redistribution and charge loss, even if the same initial Vfb is considered in charge retention experiments. While the charge loss through tunnel oxide is a DT, the charge loss through alumina depends on temperature and it is the main component of the charge loss in retention experiments for longer time.

On the impact of silicon nitride technology on charge trap NAND memories

The aim of this work is to study the impact of silicon nitride deposition/treatment technologies on charge trap (CT) nonvolatile memory performances. The authors have found that the technology modifies the charge trapping behavior with a one to one correlation between write/erase and charge retention characteristics. In particular, they used rapid thermal chemical vapor deposition techniques to obtain films with different compositions, but they were not able to improve CT performances with respect to standard low pressure chemical vapor deposition (LPCVD). Besides, an in situ steam generated treatment applied to standard LPCVD silicon nitride modifies the film properties inducing a lower programming efficiency, but improving charge retention characteristics.

Evaluation of HfLaOx as Blocking Layer for Innovative Nonvolatile Memory Applications

In this paper, a study of a La-based high-k oxide to be employed as blocking oxide in future non-volatile scaled memory devices is presented. Hf1-xLaxOy deposited by atomic layer deposition is considered. In order to allow the integration of this material, its chemical interaction with an Al2O3 cap layer has been studied. Moreover, the electrical characteristics have been evaluated after integration in capacitor structures. The rare earth-based ternary oxide presents promising characteristics to be a good candidate as active dielectric for non volatile memory devices.

Etch Rate Profile Characterization of High-κ Materials

High-κ materials are good candidates to replace the ONO (Oxide-Nitride-Oxide) stack in next generation flash memories. Starting from the 45 nm node 4-6 nm EOT (Equivalent Oxide Thickness) is required for the inter-poly dielectric, but, below 10-12 nm, conventional ONO stacks do not ensure acceptable charge retention properties because of the high leakage currents [1]. Most of the candidate high-κ materials for the ONO stack replacement show poor thermal stability properties, thus a deep comprehension of the structural evolution upon the thermal treatments is important to understand what material is more suitable for the integration in the NVM process flow.