R. Vaidyanathan

Adaptive image filtering using run-time reconfiguration

In adaptive image filtering, the coefficients of the filtering window can change in response to local conditions as the window moves from pixel to pixel over an image. This appears to preclude a solution approach involving run-time reconfiguration (RTR), as efficient use of RTR depends on a sufficient stretch of computing time between reconfiguring phases. This paper applies RTR to solve the adaptive image filtering problem by capitalizing on the regular appearance of each pixel in multiple filtering windows. We describe our approach and present simulation results demonstrating its merit.

Scaling simulation of the fusing-restricted reconfigurable mesh

This paper deals with the ability of a model to adapt algorithm instances of different sizes to run on a given model size without significant loss of efficiency. The overhead in simulating a step of a large instance of the model on a smaller instance can quantify this ability. A reconfigurable mesh (R-Mesh) can use its bus structure as a computational resource, presenting an obstacle to efficiently scaling down algorithms to run on a smaller R-Mesh. We construct a scaling simulation of a Fusing-Restricted Reconfigurable Mesh (FR-Mesh), a version of the R-Mesh. The overhead of this simulation depends only on the simulating machine size and not on the simulated machine size. Previously, the R-Mesh was not known to admit such a simulation overhead without significantly reducing its computational power. The small overhead holds importance for flexibility in algorithm design and for running algorithms with various input sizes on an available model of given size. The results of this paper extend to a variety of concurrent write rules and also translate to an improved scaling simulation of an unrestricted R-Mesh.

Reconfigurable Implementation of Wavelet Integer Lifting Transforms for Image Compression

Modern digital image processing requires powerful data compression algorithms to allow the data to be efficiently transferred from the host to end users (and back again). A typical 512times512 grayscale image of uncompressed data requires more than quarter of a million bytes. Current image compression standards like JPEG2000 and the FBI WSQ (wavelet scalar quantization) use wavelet transforms with quantization to compress still images, which reconstruct with high accuracy. This paper considers a number of popular 9/7 wavelet transform architectures. High level software models are developed for these transforms to validate their effectiveness. These software models are modified and evaluated as reversible integer wavelet lifting transforms. Further, using a virtual hardware design targeted to reconfigurable FPGA technology these transforms are implemented into a 2D discrete wavelet transform (DWT) image processor with DDR SDRAM operating at core speeds of 200+ MHz. Finally, our Matlab and Maple models perform the validation of wavelet lifting transforms

On the communication capability of the self-reconfigurable gate array architecture

The self-reconfigurable gate array (SRGA) architecture consists of an array of processing elements connected by row and column trees. In this paper, we study the communication capability of this interconnection fabric. We derive a necessary condition for any set of k one-to-one communications to be performed in t steps, for any 1 ? t ? k. Next we identify a property of the communication set, called partitionability, for which this necessary condition is sufficient as well. Then we show two classes of communication sets to possess this property. As a special case of one of these results, we show that the set of 1-step communications of a segmentable bus requires at most two steps on the SRGA architecture. This result implies that the communication ability of the bit model HV-R-Mesh, a special case of the bit model R-Mesh, can be emulated by the SRGA architecture without signifficant overhead.

Constant Time Graph and Poset Algorithms on the Reconfigurable Multiple Bus Machine

The Reconfigurable Multiple Bus Machine (RMBM) is a model of parallel computation based on reconfigurable buses. In this paper, vie present constant time RMBM algorithms for a collection of basic, graph problems that include, lowest common ancestors and Euler tour related problems (for trees) and shortest path and connectivity related problems (for general graphs). We also present results for some poset and lattice problems. All algorithms are at least as efficient or more efficient in terms of processors than corresponding PARBUS algorithms.

Optimally scaling permutation routing on reconfigurable linear arrays with optical buses

We present an optimal and scalable permutation routing algorithm for three reconfigurable models based on linear arrays that allow pipelining of information through an optical bus. Specifically, for any P/spl les/N, our algorithm routes any permutation of N elements on a P-processor model optimally in O(N/P) steps. This algorithm extends naturally to one for routing h-relations optimally in O(h) steps. We also establish the equivalence of the three models, LARPBS, LPB, and POB. This implies an automatic translation of algorithms (without loss of speed or efficiency) among these models.

An optimal multiple bus network for fan-in algorithms

We consider a class of algorithms called fan-in algorithms, with numerous applications in problems involving semigroup operations. We present a multiple bus network (MBN) that runs any fan-in algorithm in optimal number of steps. The degree and loading of this MBN are each 3. We prove that the product of the degree and loading of any MBN that runs a fan-in algorithm in optimal time is at least 9. This establishes the proposed MBN to be optimal.

A scalable and efficient algorithm for computing the city block distance transform on reconfigurable meshes

The distance transform is a basic operation in computer vision, pattern recognition and robotics. In this paper, we consider the city block (L 1 ) distance metric. An algorithm for computing the city block distance transform on reconfigurable meshes is proposed in this paper. The time complexity and scalability of the algorithm are analysed. The results indicate that the algorithm is scalable and efficient.

Bus-Based Tree Structures for Efficient Parallel Computation

We propose a class of new multiprocessor structures called bus based trees (BBTs) that are based on multiple buses. We show that a BBT can simulate a tree machine optimally. We also discuss optimal VLSI layouts for the BBT and show that the BBT can be used as a building block to construct new powerful parallel computing structures.

Configuring the circuit switched tree for multiple width communications

Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The circuit switched tree (CST) is an important interconnects used to implement such architectures. A CST consists of processing elements (PEs) and switches. PEs communicate among themselves using the links of the tree. A key component for successful communication is scheduling individual communications and the configuration of the CST switches. This paper presents a scheduling and configuration algorithm for communications on a CST where conflicts force multiple rounds of routing to perform all communications. The paper also explains how to apply the algorithm to two important classes of communications, well-nested and monotonic, for which the algorithm is optimal and efficient. The algorithm is distributed and requires only local knowledge, yet it captures the global picture to ensure proper communication.