R. W. Mountain

Silicon graphoepitaxy using a strip‐heater oven

Silicon graphoepitaxy has been achieved using a strip‐heater oven and a sample configuration consisting of a relief grating in a SiO2 substrate, a deposited amorphous silicon film, and a deposited SiO2 overlayer or ’’cap.’’ The resulting films are free of cracks and superior in crystallographic orientation and surface smoothness to graphoepitaxial films produced by laser crystallization. Enhancement‐mode, n‐channel, insulated polysilicon gate field‐effect transistors were fabricated and gave surface mobilities of 400 cm2/V sec at a p doping of 1016 cm−3. A SiO2 cap, either intentionally deposited or produced by laser crystallization in the presence of oxygen, was found to be necessary for Si graphoepitaxy. We attribute this effect to shear stresses produced by the SiO2 cap during crystallization.

Improved techniques for growth of large‐area single‐crystal Si sheets over SiO2 using lateral epitaxy by seeded solidification

Continuous single‐crystal Si sheets over SiO2 with areas of several square centimeters have been produced from poly‐Si films by the LESS technique (lateral epitaxy by seeded solidification). Seeding is achieved either with a narrow stripe opening in a recessed SiO2 layer on a single‐crystal Si substrate or with an external single‐crystal Si seed. N‐channel metal‐oxide‐semiconductor field‐effect transistors (MOSFET’s) fabricated in these films exhibit surface electron mobilities as high as 700 cm2/V s.

n‐channel deep‐depletion metal‐oxide‐semiconductor field‐effect transistors fabricated in zone‐melting‐recrystallized polycrystalline Si films on SiO2

n‐channel deep‐depletion mode metal‐oxide‐semiconductor field‐effect transistors (MOSFET’s) have been fabricated in Si films prepared by zone‐melting recrystallization of chemical‐vapor deposited (CVD) polycrystalline Si deposited on SiO2‐coated Si substrates. The transistors exhibit surface electron mobility in the range of 600–700 cm2/Vs, comparable to values for devices fabricated in single‐crystal Si. Measurements of electron mobility as a function of gate bias voltage indicate that the mobility is nearly constant throughout the depth of the recrystallized Si films. Mobility of 650–700 cm2/Vs at the lower Si‐SiO2 interface and subthreshold source‐drain leakage current of a few pA/μm (channel width) have been measured.

Characterization, Control, and Reduction of Subboundaries in Silicon on Insulators

Subboundaries are the major crystalline defects in thin semiconductor films produced by zone-melting recrystallization (ZMR). Using transmission electron microscopy (TEM) and chemical etching we have analyzed the angular discontinuity and defect structure of subboundaries in ZMR Si films. Annealing in oxygen has resulted in the elimination of dislocation bands from sizable regions of some films. Calculations suggest that cellular growth due to constitutional supercooling may not occur in some Si ZMR.

Thin‐film transistors fabricated in solid‐phase‐recrystallized Si films on fused silica substrates

Solid‐phase recrystallization of Si films prepared by chemical vapor deposition on fused silica substrates has been accomplished by transient heating on a graphite strip heater. This process increases the grain size from ∼50 nm to ∼1 μm. Thin‐film transistors fabricated in the recrystallized films exhibit surface electron mobilities of 15–20 cm2/V s and on:off current ratios in excess of 105 for a voltage swing of 10 V.

Zone-Melting Recrystallization of Semiconductor Films

The use of zone melting recrystallization (ZMR) to prepare large-grain(and in some cases single-crystal) semiconductor films is reviewed, with emphasis on recent work on Si on SiO 2 . Encapsulants are generally required to minimize contamination and decomposition, induce a crystalline texture,improve surface morphology and prevent agglomeration. In the case of Si, the solid-liquid interface is faceted, which gives rise to subboundaries. These can be entrained by laterally modulating the temperature through the use of an optical absorber on top of the encapsulant. Control of thermal gradients and in-plane crystallographic orientation are important for reliable entrainment.

Merged CMOS/bipolar technologies and microwave MESFETs utilizing zone-melting-recrystallized SOI films

Two merged CMOS/bipolar technologies utilizing SOI structures have been demonstrated. In each case a single sequence of processing steps was used to fabricate fully isolated CMOS devices and vertical bipolar transistors on the same Si wafer. The CMOS devices were fabricated in a zone-melting-recrystallized SOI film, while the bipolar devices were fabricated either in the SOI film or in epitaxial Si layers grown selectively on the Si substrate. Good electrical characteristics were obtained for the CMOS devices and for both SOI and epitaxial bipolar devices. In addition, microwave MESFETs have been fabricated in zone-melting-recrystallized Si films on bulk fused-silica substrates. These devices exhibited maximum frequency of oscillation of 8-14 GHz. At 1.2 GHz, an optimum noise figure of 2.5 dB and associated gain of 10.4 dB were measured.