C. K. Chen

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

Simulation of Photonic Band Gaps in Metal Rod Lattices for Microwave Applications

We have derived the global band gaps for general two-dimensional (2D) photonic band gap (PBG) structures formed by square or triangular arrays of metal posts. Such PBG structures have many promising applications in active and passive devices at microwave, millimeter wave, and higher frequencies. A coordinate-space, finite-difference code, called the photonic band gap structure simulator (PBGSS), was developed to calculate complete dispersion curves for lattices for a series of values of the ratio of the post radius (r) to the post spacing (a). The fundamental and higher frequency global photonic band gaps were determined numerically. These universal curves should prove useful in PBG cavity design. In addition, for very long wavelengths, where the numerical methods of the PBGSS code are difficult, dispersion curves were derived for the transverse-magnetic (TM) mode by an approximate, quasi-static approach. Results of this approach agree well with the PBGSS code for r/a<0.1. The present results are compared...

Long-wavelength Ge/sub x/Si/sub 1-x//Si heterojunction infrared detectors and 400*400-element imager arrays

Heterojunction Ge/sub x/Si/sub 1-x//Si internal photoemission infrared detectors exhibiting nearly ideal thermionic-emission dark-current characteristics have been fabricated with cutoff wavelengths out to 16 mu m. High-quality imaging without uniformity correction has been demonstrated in the long-wavelength infrared (LWIR) spectral band for 400*400-element focal plane arrays consisting of Ge/sub 0.44/Si/sub 0.56/ detectors with a cutoff wavelength of 9.3 mu m and monolithic charged-coupled-device readout circuitry. The Ge/sub 0.44/Si/sub 0.56/ composition was chosen in order to obtain a barrier height low enough to yield a cutoff length within the LWIR band, but high enough to permit low dark-current operation at about 50 K.<<ETX>>

Sub-100 nm metrology using interferometrically produced fiducials

Pattern-placement metrology plays a critical role in nanofabrication. Not far in the future, metrology standards approaching 0.2 nm in accuracy will be required to facilitate the production of 25 nm semiconductor devices. They will also be needed to support the manufacturing of high-density wavelength-division-multiplexed integrated optoelectronic devices. We are developing a new approach to metrology in the sub-100 nm domain that is based on using phase-coherent fiducial gratings and grids patterned by interference lithography. This approach is complementary to the traditional mark-detection, or “market plot” pattern-placement metrology. In this article we explore the limitations of laser-interferometer-based mark-detection metrology, and contrast this with ways that fiducial grids could be used to solve a variety of metrology problems. These include measuring process-induced distortions in substrates; measuring patterning distortions in pattern-mastering systems, such as laser and e-beam writers; and me...

Selective tungsten silicide formation by ion‐beam mixing and rapid thermal annealing

Smooth layers of tungsten silicide have been formed on silicon substrates by deposition of a tungsten film, As+ ion implantation through the film to produce ion‐beam mixing, and rapid thermal annealing. This process has been used to form tungsten silicide selectively in patterned openings etched in the SiO2 film on oxidized Si wafers, without lateral silicide growth. Rapid thermal annealing results in the activation of the As implanted in the Si substrate, without significant redistribution, to form shallow n+‐p junctions with good electrical properties.

Ultraviolet, visible, and infrared response of PtSi Schottky-barrier detectors operated in the front-illuminated mode

The quantum efficiency of PtSi Schottky-barrier detectors has been measured as a function of wavelength from 0.23 to 7 mu m. For front-illuminated PtSi/p-Si devices operated at low temperatures, quantum efficiencies of 40 to 70% are obtained in the ultraviolet (UV) and visible regions with little loss of the infrared (IR) photoresponse that is obtained for operation in the conventional back-illumination mode. For room-temperature operation of front-illumination PtSi/n-Si devices, the quantum efficiencies are approximately the same in the UV and visible regions, but the IR response decreases abruptly beyond the Si absorption edge. Room-temperature transmission and reflection measurements have been used to determine the values of the real and imaginary parts of the complex dielectric constant for PtSi at wavelengths from 0.2 to 3 mu m. A simple model, used with these values and published values of the dielectric constant for Si, yields calculated quantum efficiencies in the UV and visible regions that agree quite well with the measured efficiencies. The temporal response of front-illuminated PtSi/p-Si detectors in the visible and IR regions is found to be fast enough for operation at video frame rates. >

Characterization and entrainment of subboundaries and defect trails in zone‐melting‐recrystallized Si films

We have studied the morphology and crystallographic angular discontinuities of subboundaries and defect trails in zone‐melting‐recrystallized Si films. These subboundaries and defect trails, which originate at the interior corners of the faceted solidification front, are classified into seven types. Evidence is presented that in‐plane stress due to temperature gradients plays a major role in causing such defects. Various schemes for entraining subboundaries and defect trails are described.

Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers

A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization

High-performance fully-depleted SOI RF CMOS

A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f/sub max/ is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-/spl mu/m gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.