Rabin Raut

Placement Algorithm in Analog-Layout Designs

Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placements

On the realization of current transfer function using voltage amplifiers

Current transfer function is a feature of current-mode filters. Current-mode filters have so far been realized principally using current amplifiers and current conveyors. Some current-mode filter architecture using operational amplifiers have also been reported. In this article it is shown that by using the principles of transposed network and nullor model for the active device, a current transfer function can be realized in a very simple way using a voltage amplifier, i.e. operational amplifier (OA). The key concept is the knowledge that each ideal (i.e. infinite gain) controlled source is exactly equivalent to a nullor. Thus, a voltage-mode filter implemented using an ideal three terminal (output, input and ground) OA can be very easily converted to a current-mode filter using the same OA. The principle has been illustrated by considering single-OA- and multi-OA-based second-order voltage-mode filters. SPICE simulation results are provided to validate the theoretical concept. Copyright

Analog module placement realizing symmetry constraints based on a radiation decoder

This paper presents a new hybrid simulated annealing (SA) and genetic algorithm (GA) approach to analog module placement. The bit-matrix chromosomal representation is employed to describe the location and orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to significantly improve the search efficiency. In addition, a radiation decoder is developed to transform an absolute coordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed in analog circuits can be easily implemented in the placement run. Use of this decoder can also drastically shrink the configuration space without degrading search opportunities. The algorithm has been tested with several benchmark circuits. The experiments show this promising algorithm makes the better performance than simpler SA or GA approaches with the satisfactory results comparable to manual placement.

Generation of new OTA-C oscillator structures using network transposition

A simple but very useful approach based on network transposition principle is presented to derive new CMOS sinusoidal oscillators using operational transconductance amplifiers and capacitors (OTA-C). The principle of mirroring to convert a three-terminal two-port network to a four-terminal fully differential network is utilized to generate fully differential OTA-C oscillator structures. The theoretical work is verified by using discrete resistors, capacitors and OTA devices.

A low power Transimpedance Amplifier using inductive feedback approach in 90nm CMOS

An inductive feedback approach for BW extension of Transimpedance Amplifiers has been proposed. The effect of parasitic capacitances of the MOS transistor has been reduced using this approach. The process of zero-pole cancellation to extend the BW of the amplifier has been explained. To demonstrate the feasibility of the technique a new transimpedance amplifier has been simulated in a well-known CMOS technology (i.e. 90nm STMicroelectronics). It achieves a 3-dB bandwidth of more than 16GHz in the presence of a 150fF photodiode capacitance and 5fF loading capacitance while only dissipating 2.2mW. Despite this low power dissipation, the amplifier shows superior noise performance.

A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs

This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed-signal integrated circuit layout designs. The proposed algorithm follows the optimization flow of a normal GA controlled by the methodology of SA. The bit-matrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to significantly improve the search efficiency. In addition, a slide-based flat scheme is developed to transform an absolute co-ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulfilled in the placement run. Use of a radiation-decoder can also drastically shrink the configuration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually. Copyright

A 2.4 GHz 82 dB/spl Omega/ fully differential CMOS transimpedance amplifier for optical receiver based on wide-swing cascode topology

A fully differential transimpedance amplifier (TIA) employing the wide-swing cascode (WSC) topology for optical receiver is designed in a TSMC 0.18/spl mu/m CMOS technology. The SpectreS simulations show a transimpedance gain of 82dB/spl Omega/ (12.6K/spl Omega/), 3-dB bandwidth of 2.4GHz, low input impedance (<50/spl Omega/), dynamic range of 66dB, equivalent input referred noise of 36pA//spl radic/(Hz) and 19.5mW power consumption with 1.8V voltage supply.

Capacitive-data links, energy-efficient and high-voltage compliant visual intracortical microstimulation system

We present in this paper a new architecture of a visual intracortical microstimulator, which is composed of an external controller providing electromagnetic energy and capacitive-link based high data rate link, and a multi-unit energy-efficient implant. The latter is composed of 2 full custom chips. The first one is a multiwaveform stimuli generator dedicated to supply microstimulation-based constant current to the second chip grouping a multichannel high-impedance microelectrode driver (MED). The stimuli generator is featured with several new power-efficient building blocks such as high-performance current mirrors, low-area source/sink current-mode digital-to-analog converters (DACs), and low-power dedicated controller. The highly-configurable MED, which provides the multi-level current (2 to 196 μA), drives an array of microelectrodes through high-voltage switches. The stimuli generator is implemented in 1.2/3.3 V IBM CMOS 0.13 μm technology. However the output MED is fabricated in DALSA 0.8 μm 5V/20V CMOS/DMOS technology. The latter supplies needed compliance voltage of 10V across high impedance (average value of 100kΩ) microelectrode-tissue interface. The silicon areas of the low-voltage and high-voltage chips are 1.75×1.75 mm2 and 4.0×4.0 mm2 respectively. Post-layout simulation results are provided to show the expected operation of the device.

A fully differential and tunable CMOS current mode opamp based on transimpedance-transconductance technique

A fully differential and tunable CMOS current opamp is described in this paper. This opamp is based on a transimpedance-transconductance circuit technique. The use of a tunable transconductance block results in a voltage-tunable current op amp. Simulation results demonstrate a high-gain which can be tuned between 70 dB and 96 dB. A high gain-bandwidth product of 145 MHz has been achieved at power consumption of less than 0.5 mW and power supply voltage of /spl plusmn/1.5 V.

A placement algorithm for implementation of analog LSI/VLSI systems

Analog macro-cell placement by nature is an NP-complete (nondeterministic polynomial-time) problem. In this paper, we present an approach following the optimization flow of normal genetic algorithm (GA) controlled by the methodology of simulated annealing. The bit-matrix representation is employed to improve the search efficiency. Moreover, a cell-slide based flat placement style satisfying the symmetry constraints is developed to drastically reduce the configuration space without degrading search opportunities. Furthermore, the dedicated cost function covers the special requirements of analog integrated circuits, including area, net length, aspect ratio, proximity, parasitic effect, etc. the algorithm parameters are studied using fractional factorial experiments and a meta-GA approach. The proposed algorithm has been tested using several analog circuits, and appears superior to the simulated-annealing approaches mostly used for analog macro-cell placement nowadays.