Yingtao Jiang

An Improved Multi-Layered Architecture and its Rotational Scheme for Large-Scale Wireless Sensor Networks

In this paper, we propose a highly scalable network architecture, named the Progressive Multi-hop Rotational Clus- tered (PMRC) structure, suitable for the construction of large- scale wireless sensor networks. In the PMRC structure, sensor nodes are partitioned into layers according to their distances (cal- culated using hop counts) to the sink node. A cluster is composed of the nodes located in the same layer and within the transmission range of the cluster head which is located in one layer up. Each cluster here actually selects two cluster heads, which makes the PMRC structure different from another multi-layered structure, MINA (4). Based on the observation that load balancing tends to help balance the energy consumption among different sensor nodes and consequently prolong the network life time, we further propose a rotational scheme functioning at two levels: 1) the two cluster heads in the same cluster rotate to receive and forward data, and 2) clusters at the same layer rotate to sense data. Exten- sive simulations have been conducted to verify the rotation scheme with two selection strategies each specially tailored for one of the two cluster heads required in the PMRC structure. These results have confirmed that the PMRC structure and its rotation scheme together can significantly prolong the node life time and reduce the number of network reconstructions compared with those obtained from a multi-layered structure with single cluster head. I. INTRODUCTION The benefits of low-cost, rapid deployment, self-organization capa- bility and cooperative data-processing have made the wireless sensor networks a practical solution for a wide range of application areas, including military, industry and commercial, environment, health and home (2), (3). The most significant challenge in sensor networks is to overcome the energy constraint since each sensor node has limited power ( ) and it is hard to replenish the power es- pecially in hazardous or hostile application scenarios. The other chal- lenge faced by sensor networks is scalability. Many applications, such as military surveillance and habitat monitoring, require the deploy- ment of large-scale sensor networks (with the number of sensor nodes in the order of hundreds or thousands, or even millions) in a large ge- ographic area, and seamless connectivity to existing infrastructures is usually required when new nodes are added. Other research work for large-scale sensor networks include (7) and (10). In (7), the SAFE protocol was proposed for data dissemination from stationary sensor nodes to mobile sink nodes in large-scale sen- sor networks. The major problems of the SAFE protocol are the large number of states to be maintained at intermediate nodes and the mul- tiple rounds of message exchanges required to set up a path. The two- tier data dissemination (TTDD) protocol (10) is another protocol for disseminating data from stationary sensor nodes to multiple mobile sinks by setting up a grid structure. However, the cost of proactively creating/maintaining the grid structure from all sources to the edge of the sensor field tends to be unbearably high for large sensor networks. In this paper, we follow the layered structure and subsequently pro- pose the Progressive Multi-hop Rotational Clustered (PMRC) struc- ture as an extension to the MINA structure (4). In a PMRC structure, a cluster is formed in the way similar to that in MINA but with a signif- icant distinction: here two cluster heads are selected for each cluster. To balance the load and the energy consumption among different sen- sor nodes, we propose a rotational scheme functioning at two levels: 1) the two cluster heads in the same cluster rotate to receive and forward data, and 2) clusters at the same layer rotate to sense data. Through simulations, we show that the PMRC structure together with its ro- tational scheme outperforms the multi-layered structure with single cluster head in node life time and hence reduce the number of network reconstructions. The rest of the paper is organized as follows. In Section II, we will describe the PMRC structure. In Section III, the problems and algo- rithms of selecting the primary cluster head and the secondary cluster head are discussed. In Section IV, simulation results are presented and discussed. Section V concludes the paper.

A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs

This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed-signal integrated circuit layout designs. The proposed algorithm follows the optimization flow of a normal GA controlled by the methodology of SA. The bit-matrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to significantly improve the search efficiency. In addition, a slide-based flat scheme is developed to transform an absolute co-ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulfilled in the placement run. Use of a radiation-decoder can also drastically shrink the configuration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually. Copyright

A placement algorithm for implementation of analog LSI/VLSI systems

Analog macro-cell placement by nature is an NP-complete (nondeterministic polynomial-time) problem. In this paper, we present an approach following the optimization flow of normal genetic algorithm (GA) controlled by the methodology of simulated annealing. The bit-matrix representation is employed to improve the search efficiency. Moreover, a cell-slide based flat placement style satisfying the symmetry constraints is developed to drastically reduce the configuration space without degrading search opportunities. Furthermore, the dedicated cost function covers the special requirements of analog integrated circuits, including area, net length, aspect ratio, proximity, parasitic effect, etc. the algorithm parameters are studied using fractional factorial experiments and a meta-GA approach. The proposed algorithm has been tested using several analog circuits, and appears superior to the simulated-annealing approaches mostly used for analog macro-cell placement nowadays.

Instrumentation of YSZ oxygen sensor calibration in liquid lead-bismuth eutectic

Liquid lead-bismuth eutectic (LBE), a good candidate for the coolant in the subcritical transmutation blanket, is known to be very corrosive to the stainless steel that transports it. Such a corrosion problem can be prevented by producing and maintaining a protective oxide layer on the exposed surface of the stainless steel. Proper formation of the oxide layer critically depends on the accurate measurement and control of the oxygen concentration in liquid LBE. An oxygen sensor calibration/measurement apparatus has been designed and built to deliberately calibrate an yttria stabilized zirconia (YSZ) oxygen sensor. A detailed description of this system with its main components and their functions is presented. Calibration curves of voltage vs. temperature, ranging from 350/spl deg/C to 550/spl deg/C, under various oxygen concentrations in liquid LBE have been obtained for the YSZ oxygen sensors, and are presented and analyzed. The characteristics of this YSZ oxygen sensor are analysed and discussed.

A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltages

One promising technique to reduce power consumption is to power a chip with multiple supply voltages. However, as noticed by M.C. Johnson and K. Roy (see ACM Trans. Design Auto. Electronic Syst., vol.2, p.227-48, 1997), multiple voltage designs can cause a number of serious layout problems. We have shown that the layout problems can be partially solved by the addition of a partitioning step into the synthesis flow. A more subtle solution to solve the layout problems requires placement also to be included in the design flow. We present a synthesis scheme, following a simulated annealing engine, to minimize power consumption and area with resources operating at multiple voltages under timing constraints. The scheme simultaneously considers many correlated factors, such as scheduling, binding, partitioning and placement, to reduce power consumption due to both functional units and interconnections between and among them. Experiments with a number of DSP benchmarks show that the proposed algorithm can achieve significant reduction in power and area.

An easy tune-up exponentially fast annealer for high-quality analog module placement

VLSI analog module placement problem is NP-complete, and both simulated Cauchy annealing and simulated Boltzmann annealing approaches are widely employed as the search engine nowadays. These approaches, however, exhibit low execution efficiency and pose high degree of difficulty in tuning. In this paper, we present a very fast simulated re-annealing placement algorithm for analog VLSI layout design. We show that this algorithm is exponentially faster than either Cauchy or Boltzmann annealing. The functionality of the re-annealing is to perform an adaptive control on the annealing schedules of multidimensional parameters. Moreover, a cell-slide-based flat placement style satisfying various symmetry constraints pertaining to analog layout design is developed to drastically reduce the solution space without degrading the search opportunities. The dedicated cost function covers the special requirements for analog integrated circuits, including area, wire length, aspect ratio, proximity, parasitic effects, etc. The proposed algorithm has been applied to layout several analog circuits, and it appears superior to the conventional approaches with significantly less amount of CPU time.