Rachid Taibi

Full characterization of Cu/Cu direct bonding for 3D integration

This paper presents the latest results on electrical characterization of wafer to wafer structures made by direct copper bonding. The bonding was achieved at room temperature, atmospheric pressure and ambient air, followed by a 200°C or 400°C post bonding anneal. Description of the 3D integration process and the test-vehicle (which is used to evaluate the impact of bonding on Cu/Cu interface reliability) are described. Daisy chains from hundreds to tens of thousand connexions were tested and showed a resistance of 79.5 mΩ per node (bonding interface + Cu lines), and a specific contact resistance of the bonding around 22.5 mΩ.μm2 was extracted. These results present patterned Cu/SiO2 direct bonding as a promising solution for high density 3D integrated stacks.

An Overview of Patterned Metal /Dielectric Surface Bonding: Mechanism, Alignment and Characterization

An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.

Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration

We investigate for the first time the reliability of the direct copper bonding process. Electromigration (EM) and Stress Induced Voiding (SIV) tests are performed on intensive 30000 daisy chains and emphasize the good behaviour facing the risk of reliability issues in Cu/Cu bonded interconnects achieved by a direct low temperature (200°C) bonding. Furthermore, a comparison between stand alone and bonded device shows that the metallic bonding interfaces do not impact on the failure mechanism during EM tests.

Low temperature direct bonding: An attractive technique for heterostructures build-up

Low temperature direct bonding has been used extensively for assembling materials or components in the microelectronics and microsystem industries. We review here some key features of this technique both from the experimental and practical point of views. We give also some indications on the physical and chemical mechanisms involved in this attractive process, to better identify the important parameters impacting the quality and reliability of the technique. We describe mechanisms and report results on Si and SiO2 bonding processes. Emphasis is put on improvements that allow obtaining strong and high quality bonding in low temperature process. We demonstrate that direct bonding can be applied as well to metal bonding, mainly to obtain conductive bonding, provided an efficient process can be used for surface preparation, e.g. CMP smoothing. More generally we show that direct bonding is well suited for many heterostructures via low temperature process for instance.

An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling

An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low stress high deposition rate oxide is deposited to embed the dices. A final thinning is then done to recover a flat and smooth surface before the trough silicon vias

Chip to wafer direct bonding technologies for high density 3D integration

We demonstrate chip to wafer assembly based on aligned Cu-Cu direct bonding. A collective die surface preparation for direct bonding has implemented to develop dies direct bonding, defect free. An accurate pick and place equipment was adapted to ensure a particle free environment. After a damascene-like surface preparation, chips were bonded with less than 1μm misalignment. 400°C bonded daisy chains on die to wafer structure are perfectly ohmic. Concurrently, to overcome speed limitation of pick and place technique, a self-assembly technique chip is developed. This technique is based on capillary effect for self alignment and direct bonding for assembly. A less than 1 μm alignment accuracy and a 90 per cent self assembly process yield are obtained.

Mass transport-induced failure in direct copper (Cu) bonding interconnects for 3-D integration

This paper presents the first complete electromigration study (EM tests, failure analyses, statistical analyses with lifetime extrapolation) for direct copper bonding interconnects. This study reveals excellent performances, comparable to BEoL interconnects. Nevertheless, the results show that it will be interesting to increase the precision of alignment to maximize the Cu-Cu interface in comparison of the Cu-SiO2 to ensure high activation energy and at the end a high electromigration resistance.

(Invited) An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization

Bonding is one of the key stages for 3D integration with thinning and trough silicon via. It has to respect some global constraints for these devices. For example, a low temperature process is required when the bonding is done after or during the back end of line process. When localized vertical conductive interconnections are needed, an accurate (+/1 μm) alignment during bonding is required. The bonding toughness has to be strong enough to enable post processes like thinning. The choice of the metal is also of importance and has to be in accordance with the technology of the wafers (or dice) to be bonded. Finally the bonding technology should impact as little as possible on the technology yield and cost. Since the past ten years extensive research have been done to develop a hybrid bonding that allow localized vertical conductive interconnections. This type of bonding is also of interest for devices where, light reflective plane, heat dissipation, buried conductive layers or sealing are needed such as MEMs, power devices or LEDs. Several techniques are implemented depending if it addresses a wafer to wafer or die to wafer stack. Techniques such as thermo compression with or without polymers between metal pads, with or without eutectic alloys to decrease temperature or more recently with Thiol protected surfaces[1], bumps with low temperature solders or direct bonding are the main hybridising techniques. We will review the latest developments obtained on each technique by the principal actors of the domain. Process temperature, alignment, pitch and various pro and cons will be discussed. Nevertheless, the diminution of the bonding pitch will be a limitation difficult to overcome for conventional solder joints or thermo-compression mainly because the use of an under-filling will be very difficult. For direct bonding since the whole surface is bonded at the same time this is not a problem. Several ways were investigated to realize the direct bonding of heterogeneous metal surfaces: room temperature bonding in an ultra high vacuum tool [2]. The preferred metal is copper since it is the metal for BEOL damascene processes. We have demonstrated at LETI the feasibility of a direct hydrophilic copper-copper bonding at room temperature, atmospheric pressure and ambient air without applying an external stress. The surfaces are prepared by a chemical mechanical polishing step [3, 4]. This very simple preparation allows to use standard wafer to wafer aligner equipment to obtain an alignment in the +/-1μm range. It was also implemented for die to wafer bonding [5]. TEM observations lead us to propose a bonding mechanism based on a direct bonding coupled to a diffusion bonding (fig. 1, fig. 2). X-Ray Reflectivity (XRR) analysis enables a fine resolution of Cu/Cu bonding interface electronic density, fig. 3. For post bonding anneal around 200°C, the increase of electronic density at the bonding interface indicates its sealing. This sealing will be discussed with respect to the patterned wafer parameters in addition to acoustic and infra red microscopy observations. Nevertheless the characterization method of choice is the electrical behavior of bonded daisy chains. Daisy chains with 30 000 connections with 3x3 μm contact areas were operational all over a substrate for both 200 °C and 400°C bonding annealing (fig. 4). Considering a chip size of 2 mm2, the density of interconnections is estimated around d=1,5 10/cm2. A perfect ohmic behaviour is observed for all the tested structures. A specific contact resistance around 22.5mΩ. m was extracted [6].

200°C direct bonding copper interconnects : Electrical results and reliability

Copper direct bonding is one of the most promising approaches for three dimensional integrated circuits (3D IC). This process has reached a maturity already reported in publications for wafer to wafer and die to wafer stacking. Anyway, its reliability has to be demonstrated. In this paper Electromigration (EM) and Stress Induced Voiding (SIV) tests are also performed on 200°C bonded daisy chains to investigate the reliability behaviour of such structures, first electrical tests on bonded dies is also reported.

Quartz-based vibrating MEMS fabricated using a wafer-bonding process with sealed cavities

Here we present the results of a wafer-level approach allowing the collective fabrication of gyroscope sensors based on quartz vibrating MEMS. More specifically, we focus on suspended quartz tuning fork microstructures of a desired thickness over controlled depth cavities. This approach is based on the bonding and thinning of 4-inch z-cut quartz wafer on pre-structured silicon wafer. InfraRed (IR) inspection shows a large bonded area (>98%) while structural characterizations of the thinned quartz layer indicate a crystal quality and mechanical properties equivalent to quartz bulk material. The obtained gyroscope exhibits a quality factor (Q) around 12300 at 86.6 kHz very close to quartz theoretical thermoelastic limit. This Quartz-On-Silicon (QOS) technology open the way to a new generation of highly integrated quartz devices.