Gweltaz Gaudin

Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking

This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to the planarization (e.g. CMP) of Cu-SiO2 hybrid surfaces: copper dishing and erosion need to be minimized in order to obtain high bonding quality. The bonding quality is assessed by the evaluation of bonding strength, interfacial defects, wafer-to-wafer misalignment and electrical contact resistance at the Cu-Cu interface. The bonding strength evolution with post-bond annealing is reported and discussed for the case of patterned surfaces. Scanning Acoustic Microscopy (SAM) imaging of bonding interface is performed to monitor bonded defects. Process conditions have been optimized to minimize the post bond annealing (thermal budget) at temperatures below 400°C.

An Overview of Patterned Metal /Dielectric Surface Bonding: Mechanism, Alignment and Characterization

An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.

Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment

In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.

300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut™ technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III–V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III–V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III–V compound interface.

(Invited) An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization

Bonding is one of the key stages for 3D integration with thinning and trough silicon via. It has to respect some global constraints for these devices. For example, a low temperature process is required when the bonding is done after or during the back end of line process. When localized vertical conductive interconnections are needed, an accurate (+/1 μm) alignment during bonding is required. The bonding toughness has to be strong enough to enable post processes like thinning. The choice of the metal is also of importance and has to be in accordance with the technology of the wafers (or dice) to be bonded. Finally the bonding technology should impact as little as possible on the technology yield and cost. Since the past ten years extensive research have been done to develop a hybrid bonding that allow localized vertical conductive interconnections. This type of bonding is also of interest for devices where, light reflective plane, heat dissipation, buried conductive layers or sealing are needed such as MEMs, power devices or LEDs. Several techniques are implemented depending if it addresses a wafer to wafer or die to wafer stack. Techniques such as thermo compression with or without polymers between metal pads, with or without eutectic alloys to decrease temperature or more recently with Thiol protected surfaces[1], bumps with low temperature solders or direct bonding are the main hybridising techniques. We will review the latest developments obtained on each technique by the principal actors of the domain. Process temperature, alignment, pitch and various pro and cons will be discussed. Nevertheless, the diminution of the bonding pitch will be a limitation difficult to overcome for conventional solder joints or thermo-compression mainly because the use of an under-filling will be very difficult. For direct bonding since the whole surface is bonded at the same time this is not a problem. Several ways were investigated to realize the direct bonding of heterogeneous metal surfaces: room temperature bonding in an ultra high vacuum tool [2]. The preferred metal is copper since it is the metal for BEOL damascene processes. We have demonstrated at LETI the feasibility of a direct hydrophilic copper-copper bonding at room temperature, atmospheric pressure and ambient air without applying an external stress. The surfaces are prepared by a chemical mechanical polishing step [3, 4]. This very simple preparation allows to use standard wafer to wafer aligner equipment to obtain an alignment in the +/-1μm range. It was also implemented for die to wafer bonding [5]. TEM observations lead us to propose a bonding mechanism based on a direct bonding coupled to a diffusion bonding (fig. 1, fig. 2). X-Ray Reflectivity (XRR) analysis enables a fine resolution of Cu/Cu bonding interface electronic density, fig. 3. For post bonding anneal around 200°C, the increase of electronic density at the bonding interface indicates its sealing. This sealing will be discussed with respect to the patterned wafer parameters in addition to acoustic and infra red microscopy observations. Nevertheless the characterization method of choice is the electrical behavior of bonded daisy chains. Daisy chains with 30 000 connections with 3x3 μm contact areas were operational all over a substrate for both 200 °C and 400°C bonding annealing (fig. 4). Considering a chip size of 2 mm2, the density of interconnections is estimated around d=1,5 10/cm2. A perfect ohmic behaviour is observed for all the tested structures. A specific contact resistance around 22.5mΩ. m was extracted [6].

Novel low temperature 3D wafer stacking technology for high density device integration

Low temperature 3D wafer stacking for very high density device integration is achieved using the Smart Cut™ technology and solid phase re-crystallization. Thin silicon PN bi-layers of high quality are transferred onto new handle substrate without exceeding 500°C. The current-voltage characteristics of the intrinsic PN diode are significantly improved by using low temperature solid-phase epitaxial re-growth process in combination with the Smart Cut™ technology. An original process integration scheme is described in order to minimize the diode leakage.

3D monolithic integration: Stacking technology and applications

Wafer level stacking of single crystal films enables 3D monolithic integration of electronic devices. The monolithic stacking technology based on Smart CutTM enables front end integration of large variety of devices with nanometer alignment capability; therefore it provides more degree of freedom for the designers and integration for high density and better performance. Several applications can fully take the advantage of using the monolithic 3D stacking technology.

300 mm InGaAsOI substrate fabrication using the Smart Cut TM technology

In this work we demonstrate for the first time 300 mm InGaAs on Insulator (InGaAs-OI) substrates. A 30 nm thick InGaAs layer was successfully transferred using low temperature Direct Wafer Bonding (DWB) and the Smart CutTM technology. The epitaxial growing process has been optimized to reduce the surface roughness of the InGaAs film at around 1.5 nm RMS. HR-XRD characterization on the transferred InGaAs layer indicates that the layer remains crystalline.