Rafal Dlugosz

Realization of the Conscience Mechanism in CMOS Implementation of Winner-Takes-All Self-Organizing Neural Networks

This paper presents a complementary metal-oxide-semiconductor (CMOS) implementation of a conscience mechanism used to improve the effectiveness of learning in the winner-takes-all (WTA) artificial neural networks (ANNs) realized at the transistor level. This mechanism makes it possible to eliminate the effect of the so-called ¿dead neurons,¿ which do not take part in the learning phase competition. These neurons usually have a detrimental effect on the network performance, increasing the quantization error. The proposed mechanism comes as part of the analog implementation of the WTA neural networks (NNs) designed for applications to ultralow power portable diagnostic devices for online analysis of ECG biomedical signals. The study presents Matlab simulations of the networks model, discusses postlayout circuit level simulations and includes results of measurement completed for the physical realization of the circuit.

Current-Mode Analog Adaptive Mechanism for Ultra-Low-Power Neural Networks

Neural networks (NNs) implemented at the transistor level are powerful adaptive systems. They can perform hundreds of operations in parallel but at the expense of a large number of building blocks. In the case of analog realization, an extremely low chip area and low power dissipation can be achieved. To accomplish this, the building blocks should be simple. This brief presents a new current-mode low-complexity flexible adaptive mechanism (ADM) with a strongly reduced leakage in analog memory. Input signals ranging from 0.5 to 20 μA are held for 10-50 ms, with the leakage rate from 0.2%/ms to 0.04%/ms, respectively, depending on temperature. A small storage capacitor of 200 fF enables a short write time ( <; 100 ns). A single ADM cell occupies 1400 μm2 when realized in the Taiwan Semiconductor Manufacturing Company Ltd. CMOS 0.18-μm technology. The potential application of this NN is envisioned in a mobile platform based on a wireless sensor network to be used for online analysis of electrocardiography signals.

Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology

We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. The mechanism is very fast. In a medium sized map with several hundreds neurons implemented in the complementary metal-oxide semiconductor 0.18 μm technology, all neurons start adapting the weights after no more than 11 ns. The adaptation is then carried out in parallel. This is an evident advantage in comparison with the commonly used software-realized SOMs. The circuit is robust against the process, supply voltage and environment temperature variations. Due to a simple structure, it features low energy consumption of a few pJ per neuron per a single learning pattern. In this paper, we discuss different aspects of hardware realization, such as a suitable selection of the map topology and the initial neighborhood range, as the optimization of these parameters is essential when looking from the circuit complexity point of view. For the optimal values of these parameters, the chip area and the power dissipation can be reduced even by 60% and 80%, respectively, without affecting the quality of learning.

Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18-μm technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 μm2. When operating in the L2 mode, the circuit dissipates 85 μW of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 μW from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

An advanced software model for optimization of self-organizing neural networks oriented on implementation in hardware

In this paper we present an advanced software tool designed for a multi-criteria optimization of self-organizing neural networks (SOMs) for their effective implementation in hardware. Problems that we have to deal with in this type of implementations are radically different from those that occur in only pure software realizations. Therefore, although there are many available systems to simulate NNs, they are not useful for our purposes. The proposed system allows to investigate the influence of various physical constraints on the learning process of the NN. It enables a modification of more than sixty parameters, so almost any learning scenario, as well as almost each configuration of the NN can be tested. It is possible to run multiple tests in accordance with a created lists of tasks, in which particular parameters are changed in loops with a certain range and with a given step. This allows to carry out in a relatively short time thousands of simulations for different combinations of particular parameters. Finally, it allows to select the most efficient combinations of the parameters looking from the point of view of the effective transistor level implementation.

Analog sorting circuit for the application in self-organizing neural networks based on neural gas learning algorithm

The paper presents a new, mixed analog-digital, circuit for analog sorting signals. In comparison to other circuits of this type the proposed solution offers large versatility. The main objective is its application in Neural Gas (NG) learning algorithm used to train unsupervised neural networks (NNs). However, the circuit can also be used in nonlinear processing of analog signals. It is capable of performing simultaneously several typical nonlinear operations that include Min, Max and Median filtering. The circuit offers high accuracy, however the difference between signals that can be distinguished depends on the steepness of a reference ramp signal. For example, the circuit it able to distinguish signals that differ by 10 nA if the assumed time is larger than 1 μs. Since a typical number of neurons in the NN exceeds 100-200, the circuit has been designed to sort so many input signals. The sorting operation provides us values of particular output signals, as well as the information which inputs signals deliver particular output signals. This second feature is used in case of the application of the circuit in NN. The system was implemented in the TSMC 180nm CMOS technology and verified in the HSpice environment. For 8 inputs varying in between 1 to 10 μA the circuit dissipates an average power of 250 μW.

Low power nonlinear Min/Max filters implemented in the CMOS technology

A novel, binary-tree, asynchronous, nonlinear Min/Max filter is presented in the paper. In the proposed circuit an input signal (current in this case) is first sampled in the circular delay line, controlled by a multiphase clock (8 phases in this case). In the next stage particular samples are converted to 1-bit signals with delays proportional to the values of these samples. In the following step the delay times are compared in digital binary-tree structure. The circuit has been simulated in the TSMC CMOS 0.18 μm process. It offers a precision of 99.5% at data rate of 2.5 MSamples/s and energy consumption of 0.3-1 pJ per input.

Low Power, Low Chip Area, Digital Distance Calculation Circuit for Self-Organizing Neural Networks Realized in the CMOS Technology

This paper presents a new distance calculation circuit (DCC) that in artificial neural networks is used to calculate distances between vectors of signals. The proposed circuit is a digital, fully parallel and asynchronous solution. The complexity of the circuit strongly depends on the type of the distance measure. Considering two popular measures i.e. the Euclidean (L2) and the Manhattan (L1) one, it is shown that in the L2 case the number of transistors is even ten times larger than in the L1 case. Investigations carried out on the system level show that the L1 measure is a good estimate of the L2 one. For the L1 measure, for an example case of 4 inputs, for 10 bits of resolution of the signals, the number of transistors is equal to c. 2500. As transistors of minimum sizes can be used, the chip area of a single DCC, if realized in the CMOS 180 nm technology, is less than 0.015 mm2.

Efficient transistor level implementation of selected fuzzy logic operators used in control systems

The paper presents a novel, transistor level, implementation of selected fuzzy set operators suitable for fuzzy control systems realized in low-power hardware. We propose a fully digital, asynchronous realization of basic fuzzy logic (FL) functions, such as the bounded sum, bounded difference, bounded product, bounded complement, fuzzy logic union (MAX) and fuzzy logic intersection (MIN). All of the proposed operators has been implemented in the CMOS TSMC 180nm Technology and verified by means of transistor level simulations in Hspice environment. The proposed structures of the FL functions can easily be scaled to any signal resolutions.

Low chip area, low power dissipation, programmable, current mode, 10-bits, SAR ADC implemented in the CMOS 130nm technology

In this paper we present a novel successive approximation register (SAR) analog-to-digital converter (ADC) designed for the applications that demand many such converters working in parallel in a single chip. For this reason we have put a special emphasis on a very low chip area and low power dissipation. The ADC operates in the current-mode. The digital-to-analog converter (DAC), which is one of the components of the SAR ADCs, is in this case based on a concept of a two-stage split architecture that allows to obtain higher resolutions without a substantial increase of the chip area. As a result, the circuit implemented in the IHP CMOS 130nm technology occupies the area of only 0.01 mm2. At data rate of 0.55 MSamples/s and 10-bits of resolution it dissipates an average power of 13.2 μW. The supply voltage equals 1.2 V. The proposed circuit is programmable. The 2-stage DAC is composed of 10 branches. If smaller resolutions are sufficient, we can select the branches which are used to perform the conversion. This allows to control, to some extent, data rate of the ADC and the power dissipation.