Raffaele Zambrano

A highly reliable 3-D integrated SBT ferroelectric capacitor enabling FeRAM scaling

Ferroelectric random access memories (FeRAMs) combine very attractive properties such as low-voltage operation, fast write and nonvolatility. However, unlike Flash memories, FeRAMs are difficult to scale along with the CMOS technology roadmap, mainly because of the decrease of available signal with decreasing cell area. One solution for further scaling is to integrate three-dimensional (3-D) FeCAPs. In this paper, we have integrated a 3-D FeCAP structure in a 0.35-/spl mu/m CMOS technology whereby the effective area of <1 /spl mu/m/sup 2/ single FeCAPs is increased by a factor of almost two. We show that, after optimization of the metal-organic chemical vapor deposition (MOCVD) deposition and post-anneal steps of the Sr/sub 0.8/Bi/sub 2.2/Ta/sub 2/O/sub 9/ (SBT) layer, the sidewall SBT contributes to the polarization Pr, resulting in higher Pr values for 0.81-/spl mu/m/sup 2/ three-dimensional (3-D) capacitors (2Pr/spl ap/15 /spl mu/C/cm/sup 2/) than for 1000 /spl mu/m/sup 2/ 2-D capacitors (2Pr/spl ap/10 /spl mu/C/cm/sup 2/). Moreover, these 3-D capacitors are observed to be fatigue-free and imprint-free up to 10/sup 11/ cycles (5-V square pulses), and extrapolations of retention tests indicate less than 10% Pr loss after ten years at 85/spl deg/C, which shows that sidewall SBT retains the same excellent reliability properties as 2-D capacitors. We demonstrate in this paper that the negative signal-scaling trend can be halted using 3-D FeCAPs. To our knowledge, this paper is the first report on electrical and reliability properties of integrated 3-D FeCAPs, and is a starting point for future development work on densely scaled FeRAMs.

Integration of SrBi2Ta2O9 thin films for high density ferroelectric random access memory

Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35μm CMOS technology. In a second phase, then, pos...

Challenges for Integration of Embedded FeRAMs in the sub-180 nm Regime

Ferroelectric memories (FeRAMs) are more and more using stack cells in 1T1C configuration. While none of these are already in real production, a great progress has been made when comparing these with strapped cells in 2T2C configuration. However the FeRAM community must be ready to face another challenging step in the evolution, i.e. the transition from planar to 3D capacitors. Theres no consensus on the best approach to address this issue, which is probably a must at the 130 nm node. This paper reviews the limitations of the most popular approaches, then starts comparing two possible 3D FeCap structures (pin and cup-shaped). The final sections are dedicated to the introduction of a different strategy, trying to use a evolutionary approach. This is pursued starting with the development of a “quasi planar” FeCap in 0.35 μm technology that can evolve into a “quasi 3D” one at 0.18 μm node, and in a true one for 0.13 μm (or finer) rules.

Enhanced oxidation of TiAlN barriers integrated in three-dimensional ferroelectric capacitor structures

The oxidation characteristics of TiAlN films integrated in the bottom electrode (BE) stack of three-dimensional SrBi2Ta2O9-based (SBT) ferroelectric capacitors are investigated in the range of 650–800°C. The patterned TiAlN\Ir\IrO2\Pt BE is encapsulated by a thin ferroelectric SBT film deposited by metal organic chemical vapor deposition and then crystallized ex situ at temperatures higher than 650°C in oxygen. During this annealing step the TiAlN film oxidizes from the lateral side of the patterned BE mesas. Compared to the vertical oxidation in blanket TiAlN layers, the lateral oxidation rate in our capped patterned films is much larger for similar oxidation conditions. This lateral oxidation of the TiAlN is strongly correlated with the in-film SBT stress that depends upon the deposition temperature and the thickness of the SBT film: the higher the tensile stress in the SBT, the larger the TiAlN oxidation length induced. From a kinetic study, the lateral oxygen diffusion was found to be a self-limited p...

MECHANICAL STABILITY OF Ir ELECTRODES USED FOR STACKED SrBi2Ta2O9 FERROELECTRIC CAPACITORS

ABSTRACT A simplified TiAlN\Ir bottom electrode (BE) has been applied for the integration of stacked SrBi2Ta2O9 (SBT) ferroelectric capacitors on W-plugs. In order that the W-plugs are less exposed to oxygen during the high thermal budget used for the SBT crystallization (700°C/1 h), the implementation of low O2 partial pressures was investigated. The optimization of the annealing conditions (O2 flow) was attained by using planar TiAlN\Ir\ SBT FeCAPs. It was found that the optimal O2 content was ∼20 ppm (∼10−3 Torr), attaining polarization values (Pr) as high as 7 μ C/cm2. Higher O2 partial pressures leads to SBT with inferior ferroelectric characteristics (Pr ∼ 3 μ C/cm2 in full O2 atmosphere), which correlated well with the formation of IrO2 at the Ir-SBT interface. If patterned TiAlN\ Ir BE structures are used and SBT is crystallized at the optimal O2 partial pressure, the system is no longer stable due to extended lateral oxidation of the TiAlN film, buckling of the Ir film and subsequent W-plug oxidation. These results will be explained taking into consideration the combination of high tensile stress in the SBT and the Ir films when annealed in atmospheres close to pure N2.

Driving applications for ferroelectric NVMS

Abstract Ferroelectric Memories compare favourably with other memories because they are non volatile and easy to program/erase. The main challenge to their widespread commercialization has been lack of successful and cost effective integration with CMOS technologies. Where should a company willing to do real business with these devices address its efforts? This work is dedicated to the identification of applications where Ferro NVMs have a competitive advantages over existing devices, and to an analysis of the impact of each application on design and cell architecture. Some ”recommendations“ for a viable road map are included in the final part of this work. Its likely that Ferro NVMs will first be used as embedded memories for Smart Cards and other low/medium complexity devices, i.e. high growth rate areas, where higher revenues will come from. Addressing standalone memories will be more challenging, because of density, scalability and reliability issues. For the next few years the only available market will be that of battery backed SRAMs. Low cost and power consumption will be the key requirements for memory cards and RFID devices; embedded macrocells will demand absolute compatibility with micropocessor cores; speed and die area will be relevant issues for standalone devices.

Stress evolution in integrated SrBi 2 Ta 2 O 9 ferroelectric layers

In our integration scheme, a “pseudo-3D” capacitor cell is used where the TiAlN\Ir\IrO 2 \Pt bottom electrode is patterned before SBT deposition. In order to understand how this system behaves mechanically, we have investigated the evolution of the stress of blanket Sr 1-x Bi 2+y Ta 2 O 9 (x, y

Spacers Alternatives for INTEGRATION OF (3D) STACKED SBT FeCAPs

The thermal and mechanical stability of Ir and Ir\Pt metals spacers deposited on top of Ti(Al)N\Ir\IrO2 patterned structures has been investigated in pseudo 3D stacked SrBi2Ta2O9 (SBT) capacitors. Their stability was compared to standard TEOS spacers. The high compressive stress at the edge of patterned electrodes, as a consequence of the high thermal expansion mismatch between the metals used in the electrode and TEOS, make the system mechanically unstable at the SBT crystallization conditions (700°C for 1 hour). The mechanical problems could be overcome if the same noble metals used in the electrode are incorporated as spacers. However, thermal stability during the SBT crystallization conditions is still an issue. For the case of Ir, surface oxidation decreases the SBT polarization values. In the case of Ir\Pt, Ir diffuses through Pt and oxidizes, leading to unstable patterned structures and to the oxidation of the Ti(Al)N layer.