Raghuram S. Tupuri

A novel functional test generation method for processors using commercial ATPG

As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper describes a novel method for hierarchical functional test generation for processors which targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Applying the technique to benchmark processor designs, we were able to obtain test efficiencies for the embedded modules of the processors which were extremely close to what the commercial ATPG could do with complete access to the module. The hierarchical approach used produced this result, using the same commercial tool, but required a CPU time several orders of magnitude less than when using a conventional, flat view of the circuit.

Test generation for Gigahertz processors using an automatic functional constraint extractor

As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious problem. One solution is a novel method for functional test generation in which a transformed module is built manually, and which embodies functional constraints described using virtual logic. Test generation is then performed on the transformed module using commercial tools and the transformed module patterns are translated back to the processor level. However, the technique is useful only if the virtual logic can be generated automatically. This paper describes an automatic functional constraint extraction algorithm and a procedure to build the transformed module. We describe the tool, FALCON, used to extract the functional constraints of a given embedded module from a Verilog RTL model. The constraint extraction for embedded modules of benchmark processors using FALCON takes only a few seconds. We show that this method can generate functional patterns in a time several orders of magnitude less than one using a conventional, flat view of the circuit.

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

Sequential Automatic Test Pattern Generation is extremely computation intensive and produces acceptable results only on relatively small designs. Hierarchical approaches that target one module at a time and use ad-hoc abstractions for the rest of the design, have shown promising results in reducing the test generation complexity. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical test generation. The technique to systematically obtain a “constraint slice” for each embedded module under test within a design, is described in detail. The technique has been incorporated in an automated tool for Verilog designs, and results on large benchmark circuits show the significant benefits of the approach.

Hierarchical test generation for systems on a chip

The rapid increase in functionality on a single chip in the last few years has increased the gap between the complexity of the design and the capability of commercial test tools. In particular the test needs for systems on a chip (SOC) are not addressed by existing tools. Because some of the cores integrated on a single SOC may not have embedded testability features, it is not always possible to use conventional design for testability (DFT) methodologies directly. This paper presents a novel approach for generating tests for complex SOCs which targets one module (or core) at a time, by extracting its environment elegantly in the form of constraints and storing it as virtual logic. Information about the core processor and internal bus is used to reduce the size of the virtual logic so that a commercial ATPG tool can be used to generate tests. These tests are then automatically translated to system-level tests. The approach is illustrated with an example SOC based on the picoJava core.

Timing verification and delay test generation for hierarchical designs

This paper develops an effective solution for timing verification and delay test generation at the full chip level by exploiting the hierarchy in large designs. Currently, timing verification can only be done at the module level. We consider the timing verification problem when a module is instantiated in a larger design, where the module-level critical paths might no longer hold. In order to check whether a module-level critical path is true at the chip level, we use a fault injection circuit where detecting a stuck-at fault in this circuit will result in a pair of vectors which sensitize the critical path in the module. Unfortunately, existing sequential automatic test pattern generators (ATPG) cannot deal with complete chip designs in generating tests using the above approach. Therefore, we use a hierarchical test generation approach which abstracts the rest of the large chip into just the logic behavior relevant to the embedded module. This resulting reduction in complexity allows us to identify chip-level critical paths in large designs and to find delay tests for sensitizing these true critical paths. Experimental results confirm that the proposed technique is able to validate all the module-level critical paths in processor designs and show that most of the module-level critical paths are false at the chip level, while commercial ATPG at the full-chip level aborts in all the cases.

A novel hierarchical test generation method for processors

This paper describes a novel method for hierarchical functional test generation for processors. This method targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Since the commercial tools are unable to deal with the entire design, functional constraints are first extracted for the module. The extracted constraints are described in Verilog/VHDL and synthesized to the gate level. Then a commercial sequential ATPG is used to generate module level test vectors for faults within the module. Finally, these module level vectors are translated to processor level functional vectors and fault simulated to verify that the same coverage is obtained. Applying the technique to a benchmark processor design, we were able to obtain a test efficiency for the embedded ALU of the processor which was extremely close to what the commercial ATPG could do with complete access to the module.

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.

A comprehensive fault model for deep submicron digital circuits

Identifies the broad categories of defects which need to be considered in DSM technologies. We show that many of these defects cannot be detected using existing fault models and test approaches, and propose a new fault model for DSM circuits which incorporates logic levels as well as path delay information to deal with both functionality and performance. We show that tests derived using this model can be used to effectively screen chips for defects which affect the functionality and performance of the chips, and that the approach reduces the test costs and defect levels when compared with conventional approaches. Experimental results on large benchmark circuits are used to demonstrate the usefulness of the approach.

Delay constrained register transfer level dynamic power estimation

We present a top-down technique to estimate the average dynamic power consumption of combinational circuits at the register transfer level. The technique also captures the power-delay characteristics of a given combinational circuit. It uses the principles of logical effort to estimate the variation in capacitance, and a combination of existing techniques to estimate the variation in activity, over the delay curve of operation of the circuit. The technique does not involve post-estimation characterization and is applicable across technology nodes. The estimated power obtained from our method shows good accuracy with respect to the power obtained from a commercial gate-level power estimation tool.