Rainer Dorsch

Accumulator based deterministic BIST

Most built-in self test (BIST) solutions require specialized test pattern generation hardware which may introduce significant area overhead and performance degradation. Recently, some authors proposed test pattern generation on chip by means of functional units also used in system mode like adders or multipliers. These schemes generate pseudo-random or pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under test contains random pattern resistant faults a deterministic test pattern generator is necessary to obtain complete fault coverage. In this paper it is shown that a deterministic test set can be encoded as initial values of an accumulator based structure, and all testable faults can be detected within a given test length by carefully selecting the seeds of the accumulator. A ROM is added for storing the seeds, and the control logic of the accumulator is modified. In most cases the size of the ROM is less than the size required by traditional LFSR-based reseeding approaches.

Tailoring ATPG for embedded testing

An automatic test pattern generation (ATPG) method is presented for a scan-based test architecture which minimizes ATE storage requirements and reduces the bandwidth between the automatic test equipment (ATE) and the chip under test. To generate tailored deterministic test patterns, a standard ATPG tool performing dynamic compaction and allowing constraints on circuit inputs is used. The combination of an appropriate test architecture and the tailored test patterns reduces the test data volume up to two orders of magnitude compared with standard compacted test sets.

RESPIN++ - deterministic embedded test

RESPIN++ is a deterministic embedded test method tailored to system chips, which implement scan test at core level. The scan chains of one core of the system-on-a-chip are reused to decompress the patterns for another core. To implement the RESPIN++ test architecture only a few gates need to be added to the test wrapper. This will not affect the critical paths of the system. The RESPIN++ method reduces both test data volume and test application time up to one order of magnitude per core compared to storing compacted test patterns on the ATE. If several cores may be tested concurrently, test data volume and test application time for the complete system test may be reduced even further. This paper presents the RESPIN++ test architecture and a compression algorithm for the architecture.

Rxiensing scan chains for test pattern decompression

The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester: The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper; while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.

Task-accurate performance modeling in SystemC for real-time multi-processor architectures

We propose a framework, called virtual processing components (VPC) that permits the modeling and simulation of multiple processors running arbitrary scheduling strategies in SystemC. The granularity is given by task accuracy that guarantees a small simulation overhead

Reusing Scan Chains for Test Pattern Decompression

The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.

Adapting an SoC to ATE concurrent test capabilities

Concurrent test features are available in SoC testers to increase ATE throughput. To exploit these new features, design modifications are necessary. In a case study, these modifications were applied to the open source LEON SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several embedded cores. The concurrent test of LEON was performed on an SoC tester. The gain in test application time and area costs are quantified and obstacles in the design flow for concurrent test are discussed.

A scalable model based RTL framework zamiaCAD for static analysis

As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL-centric framework it follows the concept of non-intrusiveness. In this paper, we discuss in detail the concepts of design elaboration into the scalable design model and present an evaluation of the model for static analysis as one of the back-end applications. Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects.

Development of an audio player as system-on-a-chip using an open source platform

In this paper, we report on our experience in developing an SoC audio player using various open source components in both hardware and software parts as well as in the development process. The Ogg Vorbis audio decoder targeted for limited computing resource and low power consumption devices was developed on the free LEON SoC platform, which features a SPARC-V8 architecture compatible processor and AMBA bus. The decoder runs on the open source RTEMS operating system making use of the royalty-free open source Vorbis library. We also aim to illustrate the use of hardware/software co-design techniques. Therefore, in order to speed up the decoding process, after an analysis, a computing-intensive part of the decoding algorithm was selected and designed as an AMBA compatible hardware core. The demonstration prototype was built on the XESS XSV-800 prototyping board using GNU/Linux workstations as development workstations. This project shows that development of an SoC using an open source platform is viable and might be the preferred choice in the future.

Efficient high-level modeling in the networking domain

Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainability improve productivity. However, writing good HLMs for complex systems is still a challenging task. In the context of network controller design, modeling complexity has two major sources: (1) the functionality to handle a single connection, and (2) the number of connections to be handled in parallel. In this paper, we will propose an efficient actor-oriented modeling approach for complex systems by (1) integrating hierarchical FSMs into dynamic dataflow models, and (2) providing new channel types to allow concurrent processing of multiple connections. We will show the applicability of our proposed modeling approach to real-world system designs by presenting results from modeling and simulating a network controller for the Parallel Sysplex architecture used in IBM System z mainframes.