Lars Middendorf

Hardware synthesis of recursive functions through partial stream rewriting

Current high-level synthesis tools based on C/C++ offer only limited support for recursion and functions pointers. We present a novel approach for high-level synthesis that represents the program as a term rewriting system. Based on this concept, dynamic creation of threads, parallel recursive tasks and data-dependent branching can be supported in hardware. Complex examples are used to show the effectiveness of our method.

Dynamic task mapping onto multi-core architectures through stream rewriting

Task graphs provide an efficient model of computation for specification, analysis, and implementation of concurrent applications. In this paper, we present a novel approach for mapping the class of series-parallel task graphs onto multi-core architectures based on pattern matching. Both the topology of the graph and the state of the tasks are encoded as a stream of tokens, which is iteratively rewritten at multiple positions in parallel. Hence, our technique is most useful for compute-intensive applications that must adapt to frequently varying and unpredictable workload at runtime. Several complex examples have been evaluated on a multi-core architecture and the experimental results show the effectiveness of our approach.

A Programmable Graphics Processor based on Partial Stream Rewriting

Current graphics processing units (GPU) typically offer only a limited number of programmable pipeline stages, whose usage, data flow and topology are mostly fixed. Although a more flexible, custom rendering pipeline can be emulated using the compute functionality of existing GPUs, this approach requires to manage work queues, synchronization, and scheduling in software. In this paper, we present a hardware architecture for a novel, programmable rendering pipeline, which is based on a circulating stream of data and control tokens that are iteratively modified via pattern matching. Our architecture provides light-weight mechanisms for dynamic thread creation, lock-free synchronization, and scheduling to support recursion, dynamic shader linkage and custom primitive types. A hardware prototype, running complex examples, demonstrates the improved reconfigurability also the scalability of our graphics architecture.

A Mobile Camera-Based Evaluation Method of Inertial Measurement Units on Smartphones

In order to support navigation, gesture detection, and augmented reality, modern smartphones contain inertial measurement units (IMU) consisting of accelerometers and gyroscopes. Although the accuracy of these sensors directly affects the soundness of mobile applications, no standardized tests exist to verify the correctness of the retrieved sensor data. For this purpose, we present a novel benchmark, which utilizes the camera of the phone as a reference to estimate the quality of its sensor data fusion. Our experiments do not require special equipment and reveal significant discrepancies between different phone models.

Using stream rewriting for mapping and scheduling data flow graphs onto many-core architectures

Dataflow graphs, consisting of concurrent actors connected by communication channels, are widely used to model multimedia applications. As dataflow graphs explicitly expose the parallelism contained in the application, they yield well to synthesis for many-core architectures. However, in case of varying and unpredictable workloads, a static mapping of actors to computing resources is often infeasible, but a dynamic approach becomes challenging due to the numerous amount of actors. Our concept of stream-rewriting represents a novel execution semantics for dataflow graphs on many-core architectures, which allows for a completely dynamic binding of actors instances to processing units. In addition, we present a distributed scheduling mechanism, global resource sharing and lightweight lock-free synchronization based on pattern matching. Also, an optimized architecture for stream-rewriting is prototyped and evaluated.

Embedded Vertex Shader in FPGA

Real-time 3D visualization of objects or information becomes increasingly important in everyday life e.g. in cellular phones or mobile systems. Care should be taken in the design and implementation of 3D rendering in such embedded devices like handhelds devices in order to meet the performance requirement, while maintaining power consumption low. In this work, the design and implementation of a vertex shader on a reconfigurable hardware is presented. The main focus is placed on the efficient hardware/software partitioning of the vertex shader computation, in order to maximize the performance while maintaining a high flexibility. The resulting solution must be compatible to existing vertex shaders in oder to allow the large amount of existing program to be easylly ported to our platform. A prototype consting of a PowerPC, peripherals and some custom hardware modules is realized a on an FPGA-board. The implementation of a point rendering shows considerable speed up compared to a pure software solution.

Statistical analysis and improvement of the repeatability and reproducibility of an evaluation method for IMUs on a smartphone

An increasing number of mobile applications, like indoor-navigation or augmented reality, rely on highly accurate inertial sensor systems. However, there exists no standardized test for common inertial sensors, like accelerometers and gyroscopes to assess their accuracy. To easily determine the sensor system quality, a mobile sensor test application for smartphones was published recently. Although this test has several advantages, it lacks reproducibility and repeatability. As a remedy, we designed a special user interface that guides the operator through the test and helps judging the quality of the test conductance. While poorly conducted tests are neglected, only the meaningful ones are evaluated, so that our technology enables a more detailed analysis of the sensor systems. In this paper, we propose a statistical approach capable to distinguish between the four most important systematic errors we observed. Experiments with five state-of-the-art smartphones show that reproducibility and repeatability were significantly improved, enabling a fair comparison of the smartphone sensor systems.

Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures

Heterogeneous multi and many-core systems offer numerous benefits like reduced energy consumption and improved throughput for both high-performance and low-power applications. However, beside the design of the actual hardware architecture, also the programming of many-core systems raises several challenges. For this purpose, we extend the existing concept of stream rewriting into a model of computation for the specification of highly concurrent applications on heterogeneous systems. In particular, our approach permits to partition the stream and to bind different sections to specialized hardware components. Since stream rewriting manages a large number of active tasks without a central scheduler, we can perform the distribution and synchronization of work-items asynchronously to improve hardware utilization. Several case studies using an FPGA prototype demonstrate the scalability of our approach.

Dynamic task mapping of graphics processing applications on many-core architectures through stream rewriting

Although modern graphics processing units (GPU) contain a large number of programmable shader cores, the focus on data parallelism and also the lack of efficient on-chip communication hinder the creation of custom graphics pipelines with arbitrary topologies. Based on the concept of stream rewriting, we propose a novel many-core architecture for graphics processing, which supports dynamic scheduling of recursively expandable task graphs and graphics pipelines. In particular, the tasks and their dependencies are encoded as a token stream, which is iteratively rewritten via pattern matching on multiple cores in parallel. The scalability of the proposed hardware architecture has been evaluated using an FPGA prototype.

Scheduling of Recursive and Dynamic Data-Flow Graphs Using Stream Rewriting

Data-flow graphs, consisting of processes (actors) and communication channels, provide an efficient model of computation for analysis and implementation of highly parallel applications. We propose a novel algorithm for scheduling a large number of data-flow actors and also recursively expandable sub-graphs by encoding their state and dependencies as a token stream. The proposed execution model enables global resource sharing, dynamic instantiation of actors and provides lightweight lock-free synchronization. Hence, our approach is most useful for compute-intensive applications with frequently varying and unpredictable data rates. In addition, we present a balanced scheduling algorithm, which restricts the memory usage of dynamic and recursive data-flow graphs, while still maintaining enough concurrency to keep all execution units utilized.