Raj K. Jana

Charge transport in non-polar and semi-polar III-V nitride heterostructures

Compared to the intense research focus on the optical properties, the transport properties in non-polar and semi-polar III-nitride semiconductors remain relatively unexplored to date. The purpose of this paper is to discuss charge-transport properties in non-polar and semi-polar orientations of GaN in a comparative fashion to what is known for transport in polar orientations. A comprehensive approach is adopted, starting from an investigation of the differences in the electronic bandstructure along different polar orientations of GaN. The polarization fields along various orientations are then discussed, followed by the low-field electron and hole mobilities. A number of scattering mechanisms that are specific to non-polar and semi-polar GaN heterostructures are identified, and their effects are evaluated. Many of these scattering mechanisms originate due to the coupling of polarization with disorder and defects in various incarnations depending on the crystal orientation. The effect of polarization orientation on carrier injection into quantum-well light-emitting diodes is discussed. This paper ends with a discussion of orientation-dependent high-field charge-transport properties including velocity saturation, instabilities and tunneling transport. Possible open problems and opportunities are also discussed.

Energy-Efficient Clocking Based on Resonant Switching for Low-Power Computation

A mechanism for the reduction of dynamic energy dissipation based on energy recovery resonant switching in a computing circuit is described. The resonant circuit with controlled switches conserves energy by recovering 90% of energy that would be otherwise lost during logic state transitions. The new approach of incorporating an energy recovery storage capacitor in the resonant circuit helps to initialize the logic operation and moves the energy back and forth to the load capacitance. This energy-conserving approach preserves thermodynamic entropy, ideally preventing heat generation in the system. This proposed method is used for generating an energy-efficient “flat-topped” (quasi-trapezoidal) waveform, which is required to perform the low power digital logic computation, especially for clocking in the system applications.

Resonant clocking circuits for reversible computation

A mechanism for the reduction of dynamic energy dissipation in the computing circuit is described. The resonant circuit with controlled switches conserves the stored energy by recovering upto 90% of energy that would be otherwise lost during logic state transitions. This energy-conserving approach preserves thermodynamic entropy, ideally preventing heat generation in the system. This approach is used in a proposed resonant clocking and logic application without dynamic energy dissipation.

Sub-60 mV/decade steep transistors with compliant piezoelectric gate barriers

A novel mechanism is proposed for transistors that exploits the negative differential capacitance of piezoelectric gate barriers. Electric field induced electrostriction modulates the thickness of a piezoelectric barrier. Piezoelectricity and electrostriction in a compliant piezoelectric barrier combine to provide negative differential capacitance (NDC) with internal charge amplification. The effect of the NDC in the gate capacitor of a FET is to boost the on-current, and to provide an opportunity for switching steeper than the 60 mV/decade Boltzmann limit, both highly desirable.

Stark-effect scattering in rough quantum wells

A scattering mechanism stemming from the Stark-shift of energy levels by electric fields due to interface roughness in semiconductor quantum wells is identified. This scattering mechanism feeds off interface roughness and electric fields and modifies the well known “sixth-power” law of electron mobility degradation. This work first treats Stark-effect scattering in rough quantum wells as a perturbation for small electric fields and then directly absorbs it into the Hamiltonian for large fields. The major result is the existence of a window of quantum well widths for which the combined roughness scattering is minimum. Carrier scattering and mobility degradation in wide quantum wells are thus expected to be equally severe as in narrow wells due to Stark-effect scattering in electric fields.

Electrostrictive Tunable Capacitors and High-Performance 2D Crystal Transistors for Energy-Efficient Applications

Tunable capacitors based on electrostriction in piezoelectric barriers are presented. Electrostriction leads to a modulation of the piezoelectric barrier layer thickness caused by electrostatic attractive forces between the plates of a capacitor under applied voltage. Using this mechanism, a high range of capacitance values with a high capacitance tuning ratio, and wide tunability are obtained. Furthermore, using this electrostrictive piezoelectric capacitor in the gate stack of a two-dimensional (2D) crystal transistor, such as MoS2 transistor, a higher gate capacitance and an ON-current boost are obtained. This allows the transistor switch to operate at a smaller bias voltage in energy-efficient applications.

Transistor Switches Using Active Piezoelectric Gate Barriers

This paper explores the consequences of introducing a piezoelectric gate barrier in a normal field-effect transistor. Because of the positive feedback of strain and piezoelectric charge, internal charge amplification occurs in such an electromechanical capacitor resulting in a negative capacitance. The first consequence of this amplification is a boost in the ON-current of the transistor. As a second consequence, employing the Lagrangian method, we find that using the negative capacitance of a highly compliant piezoelectric barrier, one can potentially reduce the subthreshold slope of a transistor below the room-temperature Boltzmann limit of 60 mV/decade. However, this may come at the cost of hysteretic behavior in the transfer characteristics.

Sub-Boltzmann transistors with piezoelectric gate barriers

Scaling of field-effect transistors (FETs) is limited by the high power dissipation density, and the resulting heat generation in ICs [1]. This is due to the non-scalability of subthreshold slope (SS), i.e. the gate voltage required to change the drain current by an order of magnitude; the value is limited to SS=kTln(10)~60 mV/dec in a classical Boltzmann FET switch [2-3]. Tunneling FETs are being investigated for sub-Boltzmann switching. But even a conventional FET can potentially achieve sub-Boltzmann switching taking advantage of ferroelectric gates materials [3]. It is possible to amplify the internal channel surface potential, Ψs over the applied gate bias voltage, Vg; using negative differential capacitance (NDC) in the gate insulator. The “body factor” then reduces below unity i.e. m = ∂Vg / ∂Ψs <; 1, and hence the subthreshold slope (SS=m×60 mV/dec) can be lowered below 60 mV/dec. In this work, we show that such internal gain mechanism can also exist in piezoelectric gate materials, such as in AIN/GaN heterostructures.

Characteristics of In 0.17 Al 0.83 N/AlN/GaN MOSHEMTs with steeper than 60 mV/decade sub-threshold slopes in the deep sub-threshold region

Realization of steep sub-threshold slope (SS) transistors requires exploiting carrier transport mechanisms such as tunneling [1], and also alternative gate barrier materials (i.e. ferroelectric materials) with internal voltage gain [2]. Theoretical studies on piezoelectric barriers indicate that it is possible to achieve internal voltage amplification and steep SS in GaN MOSHEMTs by utilizing electrostriction in conjunction with piezoelectricity in AlN and InAlN [3] [4]. Less than 60 mV/decade SS was experimentally observed in GaN MOSHEMTs with InAlN barriers, in which the steep transition was tentatively correlated with the inhomogeneous distribution of polarization in the barrier [5]. However, steep SS were only observed at drain current (Id) near nA/mm regimes, which leads to difficulties in interpretation of experiment data. Understanding of the mechanism of the steep SS in these devices is still unclear and needs more characterization and modeling. In this work we demonstrate InAlN/AlN/GaN MOSHEMTs with less than 60 mV/decade SS in deep sub-threshold regions (1E-8 A/mm and below) at room temperature (RT). Drain voltage and temperature dependent characteristics are provided with analysis for advancing our understanding of this phenomenon.

A surface-potential based compact model for GaN HEMTs incorporating polarization charges

This paper introduce a method for incorporating polarization sheet charges into compact modeling in transistors. The Poisson equation is solved directly with a Dirac-delta function sheet charge at the heterojunction to obtain an analytical equation for the surface potential. This surface potential is then used to calculate the HEMT characteristics. Thus, the results of this work for the first time make an explicit connection between the material properties of the HEMT heterostructure with a surface potential based compact model through the polarization sheet charge. Furthermore, the authors have extended the intrinsic model by including field-dependent mobility and velocity saturation. The developed model should prove helpful in designing of devices and circuits.