Rajarao Jammy

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm2/Vs @ 1MV/cm) at the thinnest Tinv (1.4 nm) reported to date. These stacks are formed by capping HfO2 with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the Vt/V fb from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET Vt shift are discussed

Role of oxygen vacancies in V FB /V t stability of pFET metals on HfO 2

We demonstrate experimentally that the flatband/threshold voltages (V/sub FB//V/sub t/) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O/sub 2/ partial pressure during post-deposition N/sub 2//O/sub 2/ and/or forming gas annealing (FGA) with Re, Ru and Pt, the gate stack V/sub FB/ can change by as much as 750 mV. However, using Re as an example, it is shown that conditions can be optimized and V/sub FB//V/sub t/-tuning for pFETs can be achieved for aggressively scaled stacks. It is proposed that charge transfer from oxygen vacancies to the gate electrode, possible only for high workfunction metal gates, leads to the formation of a dipole layer near the gate which can shift V/sub FB//V/sub t/. The results indicate that V/sub FB//V/sub t/ control remains a formidable processing challenge with high workfunction metals on HfO/sub 2/.

Dipole Moment Model Explaining nFET V t Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics

A dipole moment model explaining Vt tuning in HfSiON gated nFETs is proposed and its impact on performance and reliability is presented. La, Sc, Er, and Sr dopants are utilized due to their differing electronegativities and ionic radii. These dopants tune Vt in the range of 250-600 mV. Vt tuning is found to be proportional to the net dipole moment associated with the Hf-O and rare earth (RE)-O bonds at the high-k/SiO2 interface. The magnitude of this interfacial dipole moment is determined by the electronegativities and ionic radii of the RE cations. LaOx is the most effective dopant based on Vt, mobility, and reliability,

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN/sub x/) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN/sub x/ for the NFET and ALD-WN/sub x/ for the PFET. Much enhanced drive current (I/sub d/) and transconductance (G/sub m/) values, and reduced off current (I/sub off/) characteristics were attained with ALD-MN/sub x/ gated devices over control poly-Si and PVD-MN/sub x/ devices within controllable V/sub t/ shifts. Excellent scalability of dual work function MN/sub x//high-k gate stack was demonstrated: the EOT was down to 6.6/spl Aring/ with low leakage in a low thermal budget device scheme.

Dual workfunction fully silicided metal gates

Fully silicided (FUSI), dual workfunction (WF), Ni monosilicide metal gates are demonstrated using Sb predoped polySi for setting the nFET WF and for the first time a combination of Al predoped polySi and a Ni(Pt) alloy silicide for the pFET WF. The combination of the Sb and Al predoped polySi along with the Ni(Pt)Si, allow for WFs spanning the Si band gap to within 0.2 eV of the band edges. With this large WF range the FUSI, dual WF, NiSi process is applicable for both high performance and low power CMOS applications. It is shown that the Al and Sb predoped polySi and the Ni(Pt)Si alloy have leakage currents equivalent to NiSi formed from intrinsic polySi. A fundamental voiding problem in the formation of CoSi/sub 2/ metal gates is also demonstrated, indicating the superiority of the NiSi gates.

Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates

The flatband/threshold voltages (V/sub fb//V/sub t/) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO/sub 2/ at poly-Si deposition temperatures is identified as the root cause for the poor V/sub fb//V/sub t/ control. No improvement in V/sub t/ control is obtained by engineering physically closed Si/sub 3/N/sub 4/ barrier layers on HfO/sub 2/. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V/sub fb//V/sub t/ shifts are observed with HfO/sub 2/. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al/sub 2/O/sub 3/ cap layers on silicates.

A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si (1hannel for Both N and PMOSFETs

If Si (110) channel can be used for both nMOS and pMOS FinFET, the implementation of FinFET can be simplified significantly. Electron mobility degradation at Si(110) channel of finFET has been one of the major barriers in this path. We report a creative method to improve electron and hole mobilities using a novel metal electrode induced-strain engineering, which also features the effective workfunction tuning of single metal electrode on high-k dielectric. Compared to planar SOI devices, our optimized SOI FinFETs with metal/high-k stack showed high field mobility for a (110)/lang110rang nMOSFETs, which increased almost two times. By optimizing the workfunction and the strain effect, we achieved an Ion of 930 muA/mum and 680muA/mum for nMOSFETs and pMOSFETs without implementing any other stress engineering process

Composition dependence of the work function of Ta1−xAlxNy metal gates

It is shown that the work function of Ta1−xAlxNy depends on the electrode and gate dielectric compositions. Specifically, the work function of Ta1−xAlxNy increased with SiO2 content in the gate dielectric, reaching as high as 5.0eV on SiO2; the work function was nearly 400mV smaller on HfO2. In addition, the work function decreased with increasing nitrogen content in the Ta1−xAlxNy metal gate. Increasing Al concentration increased the work function up to about 15% Al, but the work function decreased for higher Al concentrations. Chemical analysis shows that Al–O bonding at the interface correlates with the observed work function values.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)/spl sim/ -0.4 V and Vt(NFET) /spl sim/ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V/sub t/ stability) was found in the case of NiSi/ HfSi/sub x/O/sub y/ compared to the same gate electrode with HfO/sub 2/ dielectric.