Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Rajat Agarwal is active.

Publication


Featured researches published by Rajat Agarwal.


IEEE Micro | 2016

Knights Landing: Second-Generation Intel Xeon Phi Product

Avinash Sodani; Roger Gramunt; Jesus Corbal; Ho-Seop Kim; Krishna N. Vinod; Sundaram Chinthamani; Steven R. Hutsell; Rajat Agarwal; Yen-Chen Liu

This article describes the architecture of Knights Landing, the second-generation Intel Xeon Phi product family, which targets high-performance computing and other highly parallel workloads. It provides a significant increase in scalar and vector performance and a big boost in memory bandwidth compared to the prior generation, called Knights Corner. Knights Landing is a self-booting, standard CPU that is completely binary compatible with prior Intel Xeon processors and is capable of running all legacy workloads unmodified. Its innovations include a core optimized for power efficiency, a 512-bit vector instruction set, a memory architecture comprising two types of memory for high bandwidth and large capacity, a high-bandwidth on-die interconnect, and an integrated on-package network fabric. These features enable the Knights Landing processor to provide significant performance improvement for computationally intensive and bandwidth-bound workloads while still providing good performance on unoptimized legacy workloads, without requiring any special way of programming other than the standard CPU programming model.


Archive | 2005

Silent data corruption mitigation using error correction code with embedded signaling fault detection

James W. Alexander; Suresh Chittor; Dennis W. Brzezinski; Kai Cheng; Henk G. Neefs; Rajat Agarwal


Archive | 2005

Mitigating silent data corruption in a buffered memory module architecture

James W. Alexander; Suresh Chittor; Dennis W. Brzezinski; Kai Cheng; Rajat Agarwal


Archive | 2011

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Raj K. Ramanujan; Rajat Agarwal; Glenn J. Hinton


Archive | 2011

Apparatus and method for implementing a multi-level memory hierarchy

Raj K. Ramanujan; Rajat Agarwal; Kai Cheng; Taarinya Polepeddi; Camille C. Raad; David Zimmerman; Muthukumar P. Swaminathan; Dimitrios Ziakas; Mohan J. Kumar; Bassam N. Coury; Glenn J. Hinton


Archive | 2005

Fully buffered DIMM read data substitution for write acknowledgement

James W. Alexander; Rajat Agarwal; Bruce A. Christenson; Kai Cheng


Archive | 2008

MEMORY CONTROLLER USING TIME-STAGGERED LOCKSTEP SUB-CHANNELS WITH BUFFERED MEMORY

Bruce A. Christenson; Rajat Agarwal


Archive | 2008

Method, system and apparatus for reducing memory traffic in a distributed memory system

Adrian C. Moga; Rajat Agarwal; Malcolm Mandviwalla


Archive | 2006

Memory replay mechanism

James W. Alexander; Rajat Agarwal; Joaquin B. Romera


Archive | 2006

Power management using adaptive thermal throttling

Sivakumar Radhakrisnan; Suneeta Sah; William H. Nale; Rami Naqib; Howard S. David; Rajat Agarwal

Researchain Logo
Decentralizing Knowledge