Rajat Aggarwal

Solving hard instances of floorplacement

Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, embedded memories and custom RTL blocks. At current and future technology nodes, their power and performance are impacted, more than ever, by the placement of their modules. However, our experiments show that traditional techniques for placement and floorplanning, and existing academic tools cannot reliably solve the placement task.To study this problem, we identify particularly difficult industrial instances and reproduce the failures of existing tools by modifying public-domain netlists. Furthermore, we propose algorithms that facilitate floorplacement of these difficult instances. Empirically, our techniques consistently produced legal placements, and on instances where comparison is possible, reduced wirelength by 3.5% over Capo 9.4 and 14.5% over PATOMA 1.0 --- the pre-existing tools that most frequently produced legal placements in our experiments.

Architecture-specific packing for virtex-5 FPGAs

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA -- the Xilinx Virtex-5 FPGA. Two aspects of packing are discussed: 1)packing for general logic blocks, and 2 packing for large IP blocks. Virtex-5 logic blocks contain dual-output 6-input look-up-tables (LUTs). Such LUTs can implement any single logic function requiring no more than 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT output is associated with slower speed, and therefore, must be used judiciously. We present placement-based techniques for dual-output LUT packing that lead to improved area-efficiency and power, with minimal performance degradation. We then move on to address packing for large IP blocks, specifically, block RAMs and DSPs. We present a packing optimization that is widely applicable in DSP designs that leads to significantly improved design performance

Solving modern mixed-size placement instances

Physical design of modern systems-on-chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, embedded memories and custom register-transfer level (RTL) blocks. At current and future technology nodes, their power and performance are impacted, more than ever, by the placement of their modules. However, our experiments show that traditional techniques for placement and floorplanning, and existing academic tools cannot reliably solve the placement task. To study this problem, we identify particularly difficult industrial instances and reproduce the failures of existing tools by modifying pre-existing benchmark instances. Furthermore, we propose algorithms that facilitate placement of these difficult instances. Empirically, our techniques consistently produce legal placements, and on instances where comparison is possible, reduce wirelength by 13% over Capo 9.4 and 31% over PATOMA 1.0-the pre-existing tools that most frequently produce legal placements in our experiments.

Routability-Driven FPGA Placement Contest

The advances of FPGA technology and increasing size of FPGA designs pose great challenges on FPGA design tools. Deep research on FPGA physical design problems is paramount to improve industrial tools. This contest is the first ISPD contest on FPGA CAD tools. Routability driven FPGA placement, in context of large designs modern FPGA architecture, is one of the best topics to start the effort.

FPGA place & route challenges

In this paper, we describe the challenges that Place and Route tools face to implement the user designs on modern FPGAs while meeting the timing and power constraints.

Clock-Aware FPGA Placement Contest

Modern FPGA device contains complex clocking architecture on top of FPGA logic fabric. To best utilize FPGA clocking architecture, both FPGA designers and EDA tool developers need to understand the clocking architecture and design best methodology/algorithm for various design styles. Clock legalization and clock aware placement become one of the key factors in FPGA design flow. They can greatly influence FPGA design performance and routability. FPGA placement problem can get very difficult with clock legalization constraints. This years contest is a continuous challenge based on last years routability driven placement. Contestants need to design best-in-class clock aware placement approach to excel in the contest.

An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs

State-of-the-art FPGA design has become a very complex process primarily due to the aggressive timing requirements of the designs. Designers spend significant amount of time and effort trying to close the timing on their latest designs. In that timing closure methodology, Physical Synthesis plays a key role to boost the design performance. In traditional approaches, user performs placement followed by physical synthesis. As the design complexity increases, physical synthesis cannot perform all the optimization steps due to the physical constraints imposed by the placement operation. In this work, we propose an interactive methodology to perform physical synthesis in the pre-placement stage of the FPGA timing closure flow. The approach will work in two iterations of the design flow. In the first iteration, the designer will perform the regular post-placement physical synthesis operation on the design. That phase will automatically write a replayable-file which will contain information about all the optimization actions. That file also contains all the attempted optimization moves what physical synthesis deemed beneficial from QoR perspective, but was not able to accept due to the physical constraint. In the second iteration of the design flow, the designer will perform all those physical synthesis optimizations by importing the replayable file in the pre-placement stage. In addition to performing the physical synthesis flows changes, it also performs the optimizations that were not possible in the traditional physical synthesis flow. After these changes are made in the logical stage of the design flow, the crucial placement step can adapt to the optimized/better netlist structure. As a result, this approach will greatly help the users reach their challenging timing closure goal. We have evaluated the effectiveness and performance of our proposed approach on a large set of industrial designs. All these designs were targeted towards the latest Xilinx Ultrascale™ devices. Our experimental data indicates that the proposed approach improves the design performance by 4% to 5%, on an average.