Rajen Murugan

System-level SoC near-field (NF) emissions: Simulation to measurement correlation

As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

SFF-8431 12.5Gbps channel return loss (RL) failure debug: Simulation and measurement validation

The process of troubleshooting a 12.5Gbps SFF-8431 channel return loss compliance failure is described in details. Excellent simulation to measurement correlation has been achieved after capturing a capacitive dip at the package/PCB interface (“phantom” capacitance) with package and board physical layout geometries merged into one single electromagnetic simulation. Source of the “phantom” capacitance is identified and explained. Design techniques to circumvent the “phantom” capacitance and their effectiveness are evaluated through simulation studies and measurements.

System-level electro-thermal analysis of R DS(ON) for power MOSFET

A coupled-electro-thermal RDS(ON) (drain to source ON resistance) co-analysis methodology for Power MOSFET is proposed. The methodology contains two functional modules: 1) physical field solvers and 2) equivalent circuit/network solver. The field solver resolves the electrical and thermal field variables by the conventional 3D finite-element method, while the network solver can achieve accurate and efficient results by connecting the equivalent electrical, thermal and flow circuits that are extracted from the system through advanced numerical computational schemes. The integrated equivalent network can then be solved by a generic circuit solver for steady state and transient responses. The methodology is demonstrated, via simulation and measurement, on a 2.5MHz DCDC buck-boost converter. Good correlation between co-analysis methodology and laboratory measurements is achieved.

Co-Design of a High Performance 12-Bit 8GHz DDR4 Switch on a Laminate-Based CSP (Chip Scale Packaging) Technology

Multiplexer/switch ICs are key components of NVDIMM architecture that serve to isolate the host controller from the DRAM memory system. Signal integrity performance of the IC can drastically be impacted by package parasitics. In this paper we detailed a system co-design methodology that was employed to design a cost-effective DDR4 switch packaged in a laminate-based chip-scale packaging (CSP), without compromising electrical performance. The co-design simulation methodology is validated through correlation to laboratory measurements on TIs TS3DDR4000TM -- a high performance 12-bit 8GHz DDR4 switch.

Silicon-package co-design of a 45nm 200MHz bandwidth CMOS RF-to-Serdes transceiver system on chip (SoC)

In this paper we detail the silicon-package electrical co-design of a 45nm CMOS, 400MHz to 4GHz, 3GPP TDD & FDD, RF-to-Serdes base station transceiver system on chip (SoC). Electrical optimization of the silicon-package RF paths, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation flow. Laboratory measurements, on a real SoC system, are presented that validate the integrity of the modeling and simulation methodology.